LPC1778FBD144,551 NXP Semiconductors, LPC1778FBD144,551 Datasheet - Page 48

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LPC1778FBD144,551

Manufacturer Part Number
LPC1778FBD144,551
Description
ARM Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM USB 2.0
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1778FBD144,551

Rohs
yes
Core
ARM Cortex M3
Processor Series
LPC178x
Data Bus Width
32 bit
Maximum Clock Frequency
120 MHz
Program Memory Size
512 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 3.6 V
Package / Case
LQFP-144
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Interface Type
CAN, I2C, I2S, SSP
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
165
Number Of Timers
4
On-chip Dac
Yes
Program Memory Type
Flash
Factory Pack Quantity
60
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.4 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1778FBD144,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
LPC178X_7X
Product data sheet
7.13.1 Features
7.13 LCD controller
Remark: The LCD controller is available on parts LPC1788/87/86/85.
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024  768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation
– 16-bit write: 2-cycle operation (8-bit x 2-cycle)
– 32-bit write: 4-cycle operation (8-bit x 4-cycle)
AHB master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
Supports single and dual-panel color STN displays.
Supports Thin Film Transistor (TFT) color displays.
Programmable display resolution including, but not limited to: 320  200, 320  240,
640  200, 640  240, 640  480, 800  600, and 1024  768.
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized, for color STN and TFT.
24 bpp true-color non-palettized, for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
All information provided in this document is subject to legal disclaimers.
Rev. 4.1 — 15 November 2012
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
© NXP B.V. 2012. All rights reserved.
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