SIM3L144-C-GM Silicon Labs, SIM3L144-C-GM Datasheet - Page 49

• Manufacturer Part Number: SIM3L144-C-GM
• Description: ARM Microcontrollers - MCU 64KB, DC-DC, AES QFN40
• Manufacturer: Silicon Labs

Specifications of SIM3L144-C-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SiM3L1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 20
• Interface Type: I2C, SPI
• Length: 4.65 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 28
• Number Of Timers: 3
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.8 V
• Supply Voltage - Min: 1.8 V

4.8. Analog
4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0)
The SARADC0 module on SiM3L1xx devices implements the Successive Approximation Register (SAR) ADC
architecture. The key features of the module are as follows:
4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0)
The IDAC module takes a digital value as an input and outputs a proportional constant current on a pin. The IDAC
module includes the following features:
4.8.3. Low Current Comparators (CMP0, CMP1)
The Comparators take two analog input voltages and output the relationship between these voltages (less than or
greater than) as a digital signal. The low power comparator (CMPn) module includes the following features:
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Conversion complete, multiple conversion complete, and FIFO overflow and underflow flags and interrupts
Sequencer allows up to eight sources to be automatically scanned using one of four channel characteristic
Support for multiple data packing formats, including: single 10-bit sample per word, dual 10-bit samples per
Single-ended 12-bit and 10-bit modes.
Supports an output update rate of 250 k samples per second in 12-bit mode or 1 M samples per second in
10-bit mode.
Operation in low power modes at lower conversion speeds.
Selectable asynchronous hardware conversion trigger with hardware channel select.
DC offset cancellation.
Automatic result notification with multiple programmable thresholds.
Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with
programmable power-on settling and tracking time.
Non-burst mode operation can also automatically accumulate multiple conversions, but a conversion start
is required for each conversion.
supported.
Flexible output data formatting.
profiles without software intervention.
Eight-word conversion data FIFO for DMA operations.
Includes two internal references (1.65 V fast-settling, 1.2/2.4 V precision), support for an external
reference, and support for an external signal ground.
10-bit current DAC with support for four timer, up to seven external I/O and on demand output update
triggers.
Ability to update on rising, falling, or both edges for any of the external I/O trigger sources.
Supports an output update rate greater than 600 k samples per second.
Support for three full-scale output modes: 0.5 mA, 1.0 mA and 2.0 mA.
Four-word FIFO to aid with high-speed waveform generation or DMA interactions.
Individual FIFO overrun, underrun, and went-empty interrupt status sources.
word, or four 8-bit samples per word.
Support for left- and right-justified data.
Multiple sources for the positive and negative inputs, including VBAT, VREF, and 8 I/O pins.
Two outputs available: a digital synchronous latched output and a digital asynchronous raw output.
Programmable hysteresis and response time.
Falling or rising edge interrupt options on the comparator output.
6-bit programmable reference divider.
Rev 0.5
SiM3L1xx
49