SIM3L144-C-GM Silicon Labs, SIM3L144-C-GM Datasheet - Page 43

• Manufacturer Part Number: SIM3L144-C-GM
• Description: ARM Microcontrollers - MCU 64KB, DC-DC, AES QFN40
• Manufacturer: Silicon Labs

Specifications of SIM3L144-C-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SiM3L1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 20
• Interface Type: I2C, SPI
• Length: 4.65 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 28
• Number Of Timers: 3
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.8 V
• Supply Voltage - Min: 1.8 V

4.5.4. 16/32-bit Enhanced CRC (ECRC0)
The ECRC module is designed to provide hardware calculations for flash memory verification and communications
protocols. In addition to calculating a result from direct writes from firmware, the ECRC module can automatically
snoop the APB bus and calculate a result from data written to or read from a particular peripheral. This allows for
an automatic CRC result without directly feeding data through the ECRC module.
The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3). The 16-bit polynomial is fully programmable.
The CRC module includes the following features:
4.5.5. Encoder / Decoder (ENCDEC0)
The encoder / decoder module supports Manchester and Three-out-of-Six encoding and decoding from either
firmware or DMA operations.
This module has the following features:
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Support for a programmable 16-bit polynomial and one fixed 32-bit polynomial.
Byte-level bit reversal for the CRC input.
Byte-order reorientation of words for the CRC input.
Word or half-word bit reversal of the CRC result.
Ability to configure and seed an operation in a single register write.
Support for single-cycle parallel (unrolled) CRC computation for 32-, 16-, or 8-bit blocks.
Capability to CRC 32 bits of data per peripheral bus (APB) clock.
Automatic APB bus snooping.
Support for DMA writes using firmware request mode.
Supports Manchester and Three-out-of-Six encoding and decoding.
Automatic flag clearing when writing the input or reading the output data registers.
Writing to the input data register automatically initiates an encode or decode operation.
Optional output in one’s complement format.
Hardware error detection for invalid input data during decode operations, which helps reduce power
consumption and packet turn-around time.
Flexible byte swapping on the input or output data.
Rev 0.5
SiM3L1xx
43