SIM3L146-C-GQ Silicon Labs, SIM3L146-C-GQ Datasheet - Page 50

• Manufacturer Part Number: SIM3L146-C-GQ
• Description: ARM Microcontrollers - MCU 64KB, DC-DC, 32x4 LCD, AES, QFN64
• Manufacturer: Silicon Labs

Specifications of SIM3L146-C-GQ

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SiM3L1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 23
• Interface Type: I2C, SPI
• Length: 12 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 51
• Number Of Timers: 3
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.8 V
• Supply Voltage - Min: 1.8 V

SiM3L1xx
4.9. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset
state, the following occur:
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a
power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as
long as power is not lost.
The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For
VBAT Supply Monitor and power-on resets, the RESET pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal low-
power oscillator. The Watchdog Timer is enabled with the low frequency oscillator as its clock source. Program
execution begins at location 0x00000000.
All RSTSRC0 registers may be locked against writes by setting the CLKRSTL bit in the LOCK0_PERIPHLOCK0
register to 1.
The reset sources can also optionally reset individual modules, including the low power mode charge pump,
UART0, LCD0, advanced capture counter (ACCTR0), and RTC0.
50

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


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The core halts program execution.
Module registers are initialized to their defined reset values unless the bits reset only with a power-on
reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
AHB peripheral clocks to flash and RAM are enabled.
Clocks to all APB peripherals other than the Watchdog Timer and DMAXBAR are disabled.
RESET
Low Power Charge
(Alarm or Osc Fail)
Watchdog Timer
Software Reset
Supply Monitor
Pump Monitor
Missing Clock
Comparator 0
Comparator 1
RTC0 Event
Core Reset
Detector
Figure 4.4. SiM3L1xx Reset Sources Block Diagram
Reset Sources
Rev 0.5
system or module reset