C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 241

• Manufacturer Part Number: C8051F964-A-GQ
• Description: 8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F964-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

SFR Definition 17.6. EIP2: Extended Interrupt Priority 2
SFR Page = All Pages; SFR Address = 0xF7
Name
Reset
Type
Bit
Bit
7
6
5
4
3
2
1
0
PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
PWARN VDD/DC+ Supply Monitor Early Warning Interrupt Priority Control.
PDMA0 DMA0 Interrupt Priority Control.
PENC0 Encoder (ENC0) Interrupt Priority Control.
PAES0 AES0 Interrupt Priority Control.
PSPI0
Name
PPC0
PMAT
PAES0
R
7
0
This bit sets the priority of the AES0 interrupt.
0: AES0 interrupt set to low priority level.
1: AES0 interrupt set to high priority level.
This bit sets the priority of the ENC0 interrupt.
0: ENC0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
This bit sets the priority of the DMA0 interrupt.
0: DMA0 interrupt set to low priority level.
1: DMA0 interrupt set to high priority level.
Pulse Counter (PC0) Interrupt Priority Control.
This bit sets the priority of the PC0 interrupt.
0: PC0 interrupt set to low priority level.
1: PC0 interrupt set to high priority level.
Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: VDD/DC+ Supply Monitor Early Warning interrupt set to low priority level.
1: VDD/DC+ Supply Monitor Early Warning interrupt set to high priority level.
PENC0
R
6
0
PDMA0
R
5
0
PPC0
Rev. 0.5
R
4
0
Function
PSPI1
R/W
3
0
PRTC0F
R/W
2
0
C8051F96x
PMAT
R/W
1
0
PWARN
R/W
0
0
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