C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 156

• Manufacturer Part Number: C8051F964-A-GQ
• Description: 8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F964-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
SFR Definition 11.7. DMA0NCF: DMA Channel Configuration
SFR Page = 0x2; SFR Address = 0xC9
156
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
Bit
3:0
Name
Reset
7
6
5
4
Type
Bit
PERIPH[2:0]
MINTEN
ENDIAN
INTEN
INTEN
STALL
Name
R/W
7
0
MINTEN
R/W
6
0
Full-Length Interrupt Enable.
0: Disable the full-length interrupt of the selected channel.
1: Enable the full-length interrupt of the selected channel.
Mid-Point Interrupt Enable.
0: Disable the mid-point interrupt of the selected channel.
1: Enable the mid-point interrupt of the selected channel.
DMA0 Stall.
Setting this bit stalls the DMA0 transfer on the selected channel. After a
Stall, this bit must be cleared by software to resume normal operation.
0: The DMA0 transfer of the selected channel is not being stalled.
1: The DMA0 transfer of the selected channel is stalled.
Data Transfer Endianness.
This bit sets the byte order for multi-byte transfers. This is only relevant for
two or three byte transfers. The value of this bit does not matter for single
byte transfers.
0: Little Endian
1: Big Endian
Peripheral Selection of The Selected Channel.
These bits choose one of the nine DMA0 transfer functions for the selected
channel.
0000: XRAM to ENC0L/M/H
0001: ENC0L/M/H sfrs to XRAM
0010: XRAM to CRC1IN sfr
0011: XRAM to SPI1DAT sfr
0100: SPI1DAT sfr to XRAM
0101: XRAM to AES0KIN sfr
0110: XRAM to AES0BIN sfr
0111: XRAM to AES0XIN sfr
1000: AES0YOUT sfr to XRAM
STALL
R/W
5
0
ENDIAN
Rev. 0.5
R/W
4
0
Function
R
3
0
2
0
PERIPH[3:0]
R/W
1
0
0
0