S912XEP100J5VAGR Freescale Semiconductor, S912XEP100J5VAGR Datasheet - Page 747
S912XEP100J5VAGR
Manufacturer Part Number
S912XEP100J5VAGR
Description
16-bit Microcontrollers - MCU 16-bit 1000K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP100J5VAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
1000 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
S912XEP100J5VAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.4.5.5
This module allows to check for collisions on the LIN bus.
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the
transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run
when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received
data is detected the following happens:
If the bit error detect feature is disabled, the bit error interrupt flag is cleared.
Freescale Semiconductor
Output Transmit
•
•
•
•
•
Input Receive
Bit Error
Shift Register
Shift Register
The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
The transmission is aborted and the byte in transmit buffer is discarded.
the transmit data register empty and the transmission complete flag will be set
The bit error interrupt flag, BERRIF, will be set.
No further transmissions will take place until the BERRIF is cleared.
LIN Transmit Collision Detection
The RXPOL and TXPOL bit should be set the same when transmission
collision detect feature is enabled, otherwise the bit error interrupt flag may
be set incorrectly.
Receive Shift
Register
Transmit Shift
Register
Compare
Sample
Point
0
1
2
Figure 20-19. Timing Diagram Bit Error Detection
3
MC9S12XE-Family Reference Manual Rev. 1.25
Synchronizer Stage
Figure 20-18. Collision Detect Principle
4
BERRM[1:0] = 0:1
5
Bus Clock
6
7
Compare Sample Points
NOTE
8
9
RXD Pin
TXD Pin
10
11
Chapter 20 Serial Communication Interface (S12SCIV5)
BERRM[1:0] = 1:1
12
13
14
LIN Physical Interface
15
0
LIN Bus
747
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