S912XEP100J5VAGR Freescale Semiconductor, S912XEP100J5VAGR Datasheet - Page 150
S912XEP100J5VAGR
Manufacturer Part Number
S912XEP100J5VAGR
Description
16-bit Microcontrollers - MCU 16-bit 1000K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP100J5VAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
1000 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Quantity
Price
Company:
Part Number:
S912XEP100J5VAGR
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.62
2.3.63
150
Address 0x0269
Address 0x026A
Write:Never, writes to this register have no effect.
Field
Field
PTIJ
Reset
Reset
PTJ
PTJ
7-0
1
0
W
W
R
R
Port J general purpose input/output data—Data Register
This pin is associated with the TXD signal of SCI2.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data Register
This pin is associated with the TXD signal of SCI2 and chip select output CS3. The SCI function takes precedence
over the chip select and general purpose I/O function if the SCI2 is enabled. The chip select takes precedence over
the general purpose I/O.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
DDRJ7
PTIJ7
Port J Input Register (PTIJ)
Port J Data Direction Register (DDRJ)
u
0
7
7
= Unimplemented or Reserved
DDRJ6
PTIJ6
Table 2-57. PTJ Register Field Descriptions (continued)
u
0
6
6
Figure 2-61. Port J Data Direction Register (DDRJ)
Table 2-58. PTIJ Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-60. Port J Input Register (PTIJ)
DDRJ5
PTIJ5
u
0
5
5
DDRJ4
PTIJ4
u
0
4
4
Description
Description
u = Unaffected by reset
DDRJ3
PTIJ3
3
u
3
0
DDRJ2
PTIJ2
u
0
2
2
Access: User read/write
Freescale Semiconductor
DDRJ1
PTIJ1
u
0
1
1
Access: User read
DDRJ0
PTIJ0
u
0
0
0
(1)
(1)
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