S912XEP100J5VAGR Freescale Semiconductor, S912XEP100J5VAGR Datasheet - Page 715

• Manufacturer Part Number: S912XEP100J5VAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 1000K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP100J5VAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 1000 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

To calculate the output frequency in left aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
As an example of a left aligned output, consider the following case:
The output waveform generated is shown in
Freescale Semiconductor
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•
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Duty Cycle = [PWMDTYx / PWMPERx] * 100%
PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Clock Source = E, where E = 10 MHz (100 ns period)
PWMx Frequency = 10 MHz/4 = 2.5 MHz
PWMx Period = 400 ns
PWMx Duty Cycle = 3/4 *100% = 75%
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
Changing the PWM output mode from left aligned to center aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
PPOLx = 0
PPOLx = 1
Figure 19-20. PWM Left Aligned Output Waveform
MC9S12XE-Family Reference Manual Rev. 1.25
PWMDTYx
Figure
NOTE
Period = PWMPERx
19-21.
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
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