DS1086Z-11D Maxim Integrated, DS1086Z-11D Datasheet - Page 10

• Manufacturer Part Number: DS1086Z-11D
• Description: Programmable Oscillators
• Manufacturer: Maxim Integrated
• Series: DS1086r

Specifications of DS1086Z-11D

• Part # Aliases: 90-1086Z-11D

Spread-Spectrum EconOscillator
The A0, A1, A2 bits determine the 2-wire slave address.
The WC bit determines if the EEPROM is to be written
to after register contents have been changed. If
WC = 0 (default), EEPROM is written automatically after
a WRITE EE command. If WC = 1, the EEPROM is only
written when the WRITE EE command is issued. In
applications where the register contents are frequently
written, the WC bit should be set to 1. Otherwise, it is
necessary to wait for an EEPROM write cycle to com-
plete between writing to the registers. This also pre-
vents wearing out the EEPROM. Regardless of the
value of the WC bit, the value of the ADDR register is
always written immediately to EEPROM. When the
WRITE EE command has been received, the contents
of the registers are written into the EEPROM, thus lock-
ing in the register settings.
This read-only register contains a copy of the factory-
set offset (OS). This value can be read to determine the
default value of the OFFSET register when program-
ming a new master oscillator frequency.
This command is used to write data from RAM to
EEPROM when the WC bit in ADDR register is 1. See
the ADDR Register section for more details.
Since the desired frequency is not within the valid mas-
ter oscillator range of 66MHz to 133MHz, the prescaler
must be used. Valid prescaler values are 2
Figure 4. 2-Wire Data Transfer Protocol
10
Example #1: Calculate the register values needed to
generate a desired output frequency of 11.0592MHz.
______________________________________________________________________________________
SDA
SCL
CONDITION
START
Example Frequency Calculations
MSB
1
2
SLAVE ADDRESS
WRITE EE Command
RANGE Register
ADDR Register
6
7
DIRECTION
x
R/W
BIT
where x
8
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
ACK
9
equals 0 to 8 (and x is the value that is programmed
into the P3 to P0 bits of the PRESCALER register).
Equation 1 shows the relationship between the desired
frequency, the master oscillator frequency, and the
prescaler.
By trial and error, x is incremented from 0 to 8 in
Equation 2, finding values of x that yield master oscilla-
tor frequencies within the range of 66MHz to 133MHz.
Equation 2 shows that a prescaler of 8 (x = 3) and a
master oscillator frequency of 88.4736MHz generates
our desired frequency. In terms of the device register, x
= 3 is programmed in the lower four bits of the
PRESCALER register. Writing 03h to the PRESCALER
register sets the PRESCALER to 8 (and 4% peak
dither). Be aware that the J0 bit also resides in the
PRESCALER register.
Once the target master oscillator frequency has been
calculated, the value of offset can be determined.
Using Table 2, 88.4736MHz falls within both OS - 1 and
OS - 2. However, choosing OS - 1 would be a poor
choice since 88.4736MHz is so close to OS - 1’s mini-
mum frequency. On the other hand, OS - 2 is ideal
since 88.4736MHz is very close to the center of
OS - 2’s frequency span. Before the OFFSET register
can be programmed, the default value of offset (OS)
f
MASTER OSCILLATOR
1
f
MASTER OSCILLATOR = 11.0592MHz x 2
f
DESIRED
2
REPEATED IF MORE BYTES
ARE TRANSFERRED
3–7
f
MASTER OSCILLATOR
=
SIGNAL FROM RECEIVER
f
ACKNOWLEDGEMENT
MASTER OSCILLATOR
= f
8
2
DESIRED
prescaler
X
ACK
9
x prescaler = f
OR REPEATED
CONDITION
CONDITION
=
START
STOP
3
= 88.4736MHz
DESIRED
x 2
(2)
(3)
X