MAX1124EGK-TD Maxim Integrated, MAX1124EGK-TD Datasheet - Page 4

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MAX1124EGK-TD

Manufacturer Part Number
MAX1124EGK-TD
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1124EGK-TD

Number Of Channels
1
Architecture
Pipeline
Conversion Rate
250000 KSPs
Resolution
10 bit
Input Type
Single-Ended/Differential
Snr
57.1 dB
Interface Type
LVDS, Parallel
Operating Supply Voltage
1.7 V to 1.9 V
Maximum Operating Temperature
+ 85 C
Package / Case
QFN EP
Maximum Power Dissipation
657 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
Internal, External
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
internal reference, digital output pins differential R
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
Note 2: Parameter guaranteed by design and characterization; T
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
Output Offset Voltage
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low
Digital Input Voltage High
TIMING CHARACTERISTICS
CLK to Data Propagation Delay
CLK to DCLK Propagation Delay
Data Valid to DCLK Rising Edge
LVDS Output Rise-Time
LVDS Output Fall-Time
Output Data Pipeline Delay
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Total Power Dissipation
Power-Supply Rejection Ratio
(Note 3)
CC
_______________________________________________________________________________________
= OV
scale range is defined as 1023 x slope of the line.
PARAMETER
CC
= 1.8V, V
AGND
= V
OGND
SYMBOL
t
LATENCY
t
I
OV
CPDL
OV
I
P
PSRR
t
AV
t
t
OVCC
AVCC
t
CPDL
t
FALL
RISE
V
V
PDL
PDL
DISS
= 0, f
IH
IL
CC
CC
OS
-
SAMPLE
Figure 4
Figure 4
Figure 4 (Note 2)
20% to 80%, C
20% to 80%, C
f
f
f
Offset
Gain
IN
IN
IN
L
= 100MHz
= 100MHz
= 100MHz
= 100Ω ±1%, C
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
L
L
CONDITIONS
A
= 5pF
= 5pF
= T
L
MIN
= 5pF, T
to T
MAX
A
= T
.
MIN
to T
MAX
1.125
AV
0.8 x
0.92
MIN
1.7
1.7
, unless otherwise noted. ≥ +25°C
CC
TYP
2.85
1.35
460
460
220
477
1.5
1.8
1.8
1.6
1.9
A
45
8
= +25°C.)
1.310
AV
MAX
0.2 x
1.86
290
657
1.9
1.9
75
CC
UNITS
cycles
%FS/V
Clock
mV/V
mW
mA
mA
ns
ns
ns
ps
ps
V
V
V
V
V

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