MAX1124EGK-TD Maxim Integrated, MAX1124EGK-TD Datasheet - Page 10

• Manufacturer Part Number: MAX1124EGK-TD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1124EGK-TD

• Number Of Channels: 1
• Architecture: Pipeline
• Conversion Rate: 250000 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 57.1 dB
• Interface Type: LVDS, Parallel
• Operating Supply Voltage: 1.7 V to 1.9 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN EP
• Maximum Power Dissipation: 657 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal, External

1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
The MAX1124 uses a fully differential, pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a common-
mode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typi-
cal differential full-scale signal swing of 1.25V
INP and INN are buffered prior to entering each track-
and-hold (T/H) stage and are sampled when the differen-
tial sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Figure 1. MAX1124 Block Diagram
Figure 2. Simplified Analog Input Architecture
10
______________________________________________________________________________________
TO COMMON-MODE INPUT
INP
2.2kΩ
Detailed Description—Theory
CLKN
CLKP
INN
INP
2.2kΩ
COMMON-MODE
BUFFER
TO COMMON-MODE INPUT
2.2kΩ
of Operation
CONTROL
CLOCK-
DIVIDER
CLKDIV
BUFFER
INPUT
2.2kΩ
P-P
INN
AV
AGND
.
MANAGEMENT
CC
REFIO REFADJ
REFERENCE
CLOCK
T/H
QUANTIZER CORE
10-BIT PIPELINE
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 10-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital cor-
rection logic to generate the final output code. The result
is a 10-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDS-
compatible output levels. See Figure 1 for a more
detailed view of the MAX1124 architecture.
Figure 3. Simplified Reference Architecture
1V
MAX1124
ADC FULL-SCALE = REFT - REFB
DATA PORT
LVDS
REFERENCE
BUFFER
DISABLE REFERENCE
CONTROL LINE TO
BUFFER
10
REFB
REFT
AV
CC
G
DCLKP
DCLKN
D0P/N–D9P/N
ORP
ORN
REFERENCE
AMPLIFIER
SCALING
AV
CC
/2
REFIO
REFADJ
1kΩ
0.1μF