MAX1124EGK-TD Maxim Integrated, MAX1124EGK-TD Datasheet - Page 13

• Manufacturer Part Number: MAX1124EGK-TD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1124EGK-TD

• Number Of Channels: 1
• Architecture: Pipeline
• Conversion Rate: 250000 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 57.1 dB
• Interface Type: LVDS, Parallel
• Operating Supply Voltage: 1.7 V to 1.9 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN EP
• Maximum Power Dissipation: 657 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal, External

The digital outputs D0P/N–D9P/N, DCLKP/N, and
ORP/N are LVDS compatible, and data on
D0P/N–D9P/N is presented in either binary or two’s
complement format (Table 1). The T/B control line is an
LVCMOS-compatible input, which allows the user to
select the desired output format. Pulling T/B low outputs
data in two’s complement and pulling it high presents
data in offset binary format on the 10-bit parallel bus.
T/B has an internal pulldown resistor and may be left
unconnected in applications using only two’s comple-
ment output format. All LVDS outputs provide a typical
voltage swing of 0.4V around a common-mode voltage
of approximately 1.2V, and must be terminated at the
far end of each transmission line pair (true and comple-
mentary) with 100Ω. The LVDS outputs are powered
from a separate power supply, which can be operated
between 1.7V and 1.9V.
The MAX1124 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out of range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although differential LVDS reduces single-ended
transients to the supply and ground planes, capacitive
loading on the digital outputs should still be kept as low
as possible. Using LVDS buffers on the digital outputs
of the ADC when driving off-board may improve overall
performance and reduce system timing constraints.
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
Digital Outputs (D0P/N–D9P/N, DCLKP/N,
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________
ORP/N) and Control Input T /B
INPUT TERMINAL
SINGLE-ENDED
510Ω
0.1μF
50Ω
510Ω
2
3
MC100LVEL16
0.1μF
4
0.01μF
V
CLK
VGND
8
5
7
6
150Ω
150Ω
0.1μF
0.1μF
The MAX1124 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, an exter-
nal resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or pre-
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
ADC FULL-SCALE = REFT - REFB
1V
Full-Scale Range Adjustments Using the
INN
INP
REFERENCE
DISABLE REFERENCE
REFT
REFB
CONTROL LINE TO
BUFFER
CLKN
Applications Information
MAX1124
AGND
BUFFER
CLKP
Internal Bandgap Reference
AV
G
AV
CC
OGND
REFERENCE-
CC
OV
AMPLIFIER
SCALING
CC
AV
REFADJ
D0P/N–D9P/N
10
REFIO
CC
/2
0.1μF
13kΩ TO 1MΩ
13kΩ TO 1MΩ
13