SPC5646CCF0MLT1 Freescale Semiconductor, SPC5646CCF0MLT1 Datasheet - Page 7

• Manufacturer Part Number: SPC5646CCF0MLT1
• Description: 32-bit Microcontrollers - MCU 3M FLASH,25 6K RAM,CSE
• Manufacturer: Freescale Semiconductor

Specifications of SPC5646CCF0MLT1

• Rohs: yes
• Core: e200
• Processor Series: MPC5646C
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 3 MB
• Data Ram Size: 256 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 0.3 V to 6.2 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-208
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 33
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 177
• Number Of Timers: 32
• Program Memory Type: Flash
• Supply Voltage - Max: 6.2 V
• Supply Voltage - Min: 0.3 V

Table 2
Freescale
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
Clock monitor unit (CMU)
Cross triggering unit (CTU)
Cryptographic Security Engine
(CSE)
Crossbar (XBAR) switch
DMA Channel Multiplexer
(DMAMUX)
Deserial serial peripheral interface
(DSPI)
Error Correction Status Module
(ECSM)
Enhanced Direct Memory Access
(eDMA)
Enhanced modular input output
system (eMIOS)
Flash memory
FlexCAN (controller area network) Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
FlexRay (FlexRay communication
controller)
Fast Ethernet Controller (FEC)
Internal multiplexer (IMUX) SIUL
subblock
Inter-integrated circuit (I
Interrupt controller (INTC)
JTAG controller
summarizes the functions of the blocks present on the MPC5646C.
Block
2
C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
Table 2. MPC5646C series block summary
MPC5646C Microcontroller DataSheet, Rev. 5.1
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Supports the encoding and decoding of any kind of data
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
Allows to route DMA sources (called slots) to DMA channels
Provides a synchronous serial interface for communication with external devices
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels.
Provides the functionality to generate or measure events
Provides non-volatile storage for program code, constants and variables
Generates high-speed system clocks and supports programmable frequency
modulation
Provides high-speed distributed control for advanced automotive applications
Ethernet Media Access Controller (MAC) designed to support both 10 and 100
Mbps Ethernet/IEEE 802.3 networks
Allows flexible mapping of peripheral interface on the different pins of the device
data exchange between devices
Provides priority-based preemptive scheduling of interrupt requests for both
e200z0h and e200z4d cores
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
Function
Block diagram
7