SPC5646CCF0MLT1 Freescale Semiconductor, SPC5646CCF0MLT1 Datasheet - Page 54

• Manufacturer Part Number: SPC5646CCF0MLT1
• Description: 32-bit Microcontrollers - MCU 3M FLASH,25 6K RAM,CSE
• Manufacturer: Freescale Semiconductor

Specifications of SPC5646CCF0MLT1

• Rohs: yes
• Core: e200
• Processor Series: MPC5646C
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 3 MB
• Data Ram Size: 256 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 0.3 V to 6.2 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-208
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 33
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 177
• Number Of Timers: 32
• Program Memory Type: Flash
• Supply Voltage - Max: 6.2 V
• Supply Voltage - Min: 0.3 V

Electrical Characteristics
4.8
4.8.1
The device implements an internal voltage regulator to generate the low voltage core supply V
supply V
The internal voltage regulator requires external bulk capacitance (C
voltage digital supply to the device. Also required for stability is the C
54
NPN driver
Off chip
BCP68
VDD_BV
•
•
(4  10 f)
40 f
HV: High voltage external power supply for voltage regulator module. This must be provided externally through
V
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the on-chip
VREG with an external ballast (BCP68 NPN device). It is further split into four main domains to ensure noise isolation
between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA0/CFLA1: Low voltage supply for the two code Flash modules. It is shorted with LV_COR through
— LV_DFLA: Low voltage supply for data Flash module. It is shorted with LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
DD_HV_A
10
(C
(C
DD_HV_A
REGn
DEC2
Power management electrical characteristics

double bonding.
f
Voltage regulator electrical characteristics
)
)
VRC_CTRL
VSS_LV
VDD_LV
. The following supplies are involved:
power pin.
HPVDD
VDD_LV
LPVDD
100 nf
VDD_HV_A
VSS_LV
Figure 8. Voltage regulator capacitance connection
PD1 Switchable Domain
HPREG
LPREG
(FMPLL, Flash)
VDD_LV
100 nf
MPC5646C Microcontroller DataSheet, Rev. 5.1
VSS_HV
100 nf
VSS_LV
HPVDD
LPVDD
VDD_LV
Chip Boundary
100 nf
sw1 (<0.1)
VSS_LV
REGn
DEC2
) to be connected to the device to provide a stable low
PD0 (always on domain)
capacitor at ballast collector. This is needed to
CTRL
32 KB
Split
CTRL
56 KB
Split
DD_LV
from the high voltage
Split
8 KB
CTRL
Freescale