SSTU32865ET,557 NXP Semiconductors, SSTU32865ET,557 Datasheet - Page 8

• Manufacturer Part Number: SSTU32865ET,557
• Description: IC BUFFER 1.8V 28BIT SOT802-1
• Manufacturer: NXP Semiconductors

Specifications of SSTU32865ET,557

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935275069557; SSTU32865ET; SSTU32865ET

Philips Semiconductors
7. Functional description
Table 3:
[1]
Table 4:
[1]
9397 750 13799
Product data sheet
RESET
RESET
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.
L
H
H
H
H
H
H
H
H
H
H
L
0
is the previous state of the associated output.
Function table (each flip-flop)
Parity and standby function table
floating
DCS0
X or floating
X or
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
DCS0
7.1 Function table
H
H
H
H
H
X
L
L
L
L
floating
DCS1
X or
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
X or floating
DCS1
H
H
H
H
H
X
L
L
L
L
CSGATEEN
X or floating
Inputs
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
X or floating
L or H
CK
Rev. 02 — 28 September 2004
Inputs
floating
L or H
L or H
L or H
L or H
L or H
X or
CK
X or floating
L or H
floating
CK
L or H
L or H
L or H
L or H
L or H
X or
CK
Dn, DODTn,
X or floating
DCKEn
(D0 to D21)
X or floating
of inputs = H
H
H
H
H
H
X
X
X
X
X
1.8 V DDR registered buffer with parity
L
L
L
L
L
even
even
even
even
odd
odd
odd
odd
X
X
Qn
Q
Q
Q
Q
Q
Q
Q
H
H
H
H
L
L
L
L
L
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
0
0
0
0
0
0
0
X or floating
PARIN
QCS0
SSTU32865
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
X
X
0
0
0
0
0
Outputs
[1]
QCS1
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
0
0
0
0
0
PTYERR
[1]
PTYERR
PTYERR
Output
QODTn,
QCKEn
H
H
H
H
H
L
L
L
L
Q
Q
Q
Q
Q
H
H
H
H
H
L
L
L
L
L
L
8 of 29
[2] [3]
0
0
0
0
0
0
0