SSTU32865ET,557 NXP Semiconductors, SSTU32865ET,557 Datasheet - Page 18

• Manufacturer Part Number: SSTU32865ET,557
• Description: IC BUFFER 1.8V 28BIT SOT802-1
• Manufacturer: NXP Semiconductors

Specifications of SSTU32865ET,557

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935275069557; SSTU32865ET; SSTU32865ET

Philips Semiconductors
11. Test information
9397 750 13799
Product data sheet
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics: Pulse
Repetition Rate (PRR)
otherwise specified.
The outputs are measured one at a time with one transition per measurement.
Fig 8. Load circuit
Fig 9. Voltage and current waveforms; inputs active and inactive times
Fig 10. Voltage waveforms; pulse duration
(1) C
(1) I
CK inputs
V
V
V
DD
ID
IH
IL
L
includes probe and jig capacitance.
= V
tested with clock and data inputs held at V
= 600 mV
= V
REF
REF
R
test point
test point
+ 250 mV (AC voltage levels) for differential inputs. V
L
RESET
= 100
250 mV (AC voltage levels) for differential inputs. V
input
T
LVCMOS
Rev. 02 — 28 September 2004
L
= 50
10 MHz; Z
I
DD
(1)
V
DD
t
INACT
/2
V
0
10 %
ICR
CK
CK
= 50 ; input slew rate = 1 V/ns
DUT
OUT
t
W
DD
or GND, and I
1.8 V DDR registered buffer with parity
T
L
= 350 ps, 50
V
DD
V
ICR
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
t
/2
ACT
O
IL
IH
= 0 mA.
C
= GND for LVCMOS inputs.
= V
L
002aaa373
0 V
V
= 30 pF
DD
002aaa372
V
DD
SSTU32865
ID
90 %
V
V
for LVCMOS inputs.
(1)
IH
IL
20 %, unless
V
DD
002aaa371
R
R
L
L
= 1000
= 1000
18 of 29