S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 757

• Manufacturer Part Number: S9S12G64F0CLFR
• Description: 16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0CLFR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 40
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

23.3.2.4
1
Read: Anytime
Write: Anytime
23.3.2.5
Freescale Semiconductor
Module Base + 0x0003
Module Base + 0x0004
OC7M[7:0]
OC7D[7:0]
.
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
TCNT15
OC7D7
Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,
the output compare action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
Output Compare 7 Data Register (OC7D)
Timer Count Register (TCNT)
15
0
0
7
a channel 7 event, even if the corresponding pin is setup for output compare.
channel 7 event.
be transferred from the output compare 7 data register to the timer port.
TCNT14
OC7D6
14
0
0
6
Figure 23-9. Output Compare 7 Data Register (OC7D)
Figure 23-10. Timer Count Register High (TCNTH)
MC9S12G Family Reference Manual, Rev.1.23
Table 23-4. OC7M Field Descriptions
Table 23-5. OC7D Field Descriptions
TCNT13
OC7D5
13
0
0
5
TCNT12
OC7D4
12
0
0
4
Description
Description
TCNT11
OC7D3
11
0
0
3
TCNT10
OC7D2
10
0
0
2
Timer Module (TIM16B8CV3)
OC7D1
TCNT9
0
0
1
9
OC7D0
TCNT8
0
0
0
9
759