S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 217

• Manufacturer Part Number: S9S12G64F0CLFR
• Description: 16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0CLFR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 40
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

1
1
2.4.3.21
2.4.3.22
Freescale Semiconductor
Address 0x0249
Address 0x024A
Read: Anytime
Write:Never
Read: Anytime
Write: Anytime
Field
Field
PTIS
PTS
Reset
Reset
7-0
7-0
W
W
R
R
Port S general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
DDRS7
PTIS7
Port S Input Register (PTIS)
0
Port S Data Direction Register (DDRS)
0
7
7
DDRS6
PTIS6
0
0
6
6
Figure 2-23. Port S Data Direction Register (DDRS)
Table 2-41. PTIS Register Field Descriptions
Table 2-40. PTS Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
Figure 2-22. Port S Input Register (PTIS)
DDRS5
PTIS5
0
0
5
5
DDRS4
PTIS4
0
0
4
4
Description
Description
DDRS3
PTIS3
3
0
3
0
DDRS2
PTIS2
0
0
2
2
Port Integration Module (S12GPIMV1)
DDRS1
Access: User read/write
PTIS1
Access: User read only
0
0
1
1
DDRS0
PTIS0
0
0
0
0
219
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1