IDT74SSTUBF32865ABK IDT, Integrated Device Technology Inc, IDT74SSTUBF32865ABK Datasheet
IDT74SSTUBF32865ABK
Specifications of IDT74SSTUBF32865ABK
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IDT74SSTUBF32865ABK Summary of contents
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REGISTERED BUFFER WITH PARITY Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V V operation. DD All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Block Diagram V REF PARIN D0 D21 DCS0 CSGateEN DCS1 DCKE0, DCKE1 DODT0, DODT1 RESET CLK CLK 28-BIT 1:2 REGISTERED BUFFER WITH PARITY (CS ACTIVE ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Pin Configuration 160-Ball BGA TOP VIEW 28-BIT 1:2 ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Ball Assignment Signal Group Signal Name DCKE0, DCKE1, Ungated Inputs DODT0, DODT1 Chip Select Gated Inputs Chip Select Inputs DCS0, DCS1 Re-Driven Parity Input Parity Error Program Inputs Clock Inputs Miscellaneous Inputs 28-BIT ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Function Table RESET DCS0 DCS1 ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Parity and Standby Function Table RESET DCS0 DCS1 ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Operating Characteristics The RESET and CSGateEN inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Timing Requirements Over Recommended Operating Free-Air Temperature Range Symbol Parameter f Clock Frequency CLOCK t Pulse Duration; CLK, CLK HIGH or LOW W t Differential Inputs Active Time ACT t Differential Inputs Inactive ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range Parameter dV/dt_r dV/dt_f 1 dV/dt_∆ 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 28-BIT 1:2 REGISTERED BUFFER ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Parity Logic Diagram PARIN CLOCK Register Timing CLK CLK PARIN PTYERR 28-BIT 1:2 REGISTERED BUFFER WITH ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Test Circuits and Waveforms (V DUT CLK Out CLK Inputs CLK Test Point R 100 L = Test Point Simulation Load Circuit LVCMOS RESET Input t ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Test Circuits and Waveforms (V DUT Out Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% 20% dv_f dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Ordering Information IDT XX SSTUBF XX Family Temp. Range 28-BIT 1:2 REGISTERED BUFFER WITH PARITY XXX XX X Device Type Package Shipping Carrier 8 BKG 865A COMMERCIAL TEMPERATURE GRADE Tape ...
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IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...