IDT74SSTUBH32868ABKG IDT, Integrated Device Technology Inc, IDT74SSTUBH32868ABKG Datasheet - Page 14

• Manufacturer Part Number: IDT74SSTUBH32868ABKG
• Description: IC BUFFER 28BIT CONF DDR2 176BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTUBH32868ABKG

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-BGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Invert/Non-Invert
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 176
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74SSTUBH32868ABKG

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol Parameter
t
Symbol
t
PDMSS
t
t
f
PDM
t
INACT
1
2
a minimum time of t
3
of t
PDQ 2
t
t
1
2
f
MAX
ACT
t
t
PLH
PHL
CLOCK
LH
HL
t
t
SU
t
W
H
INACT
1
This parameter is not production tested.
V
V
Design target as per JEDEC specifications.
Production Test. (See Product Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
1,2
1,3
REF
REF
Max Input Clock Frequency
Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn
Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn
Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn
LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to QERR
HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to QERR
HIGH to LOW Propagation Delay, RESET↓ to Qn↓
LOW to HIGH Propagation Delay, RESET↓ to QERR↑
(max) after RESET is taken LOW.
must be held at a valid input voltage level and data inputs must be held at valid voltage levels for
data and clock inputs must be held at valid input voltage levels (not floating) for a minimum time
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup
Time
Time
Hold
ACT
DCS0 before CLK↑, CLK↓, DCS1 and CSGEN HIGH;
DCS1 before CLK↑, CLK↓, DCS0 and CSGEN HIGH;
DCS0 before CLK↑, CLK↓, DCS1 LOW and CSGEN
HIGH or LOW; DCS1 before CLK↑, CLK↓, DCS0
LOW and CSGEN HIGH or LOW
DODTn, DCKEn, PAR_IN, and data before CLK↑,
CLK↓
DCSn, DODT,n DCKEn, and data after CLK↑, CLK↓
PAR_IN after CLK↑, CLK↓
(max) after RESET is taken HIGH.
14
COMMERCIAL TEMPERATURE GRADE
V
V
Min.
DD
410
1.1
0.4
1.2
DD
Min.
1
0.6
0.5
0.5
0.4
0.4
1
= 1.8V ± 0.1V
IDT74SSTUBH32868A
= 1.8V ± 0.1V
Max.
Max.
1.75
1.5
2.4
410
1
3
3
3
10
15
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7105/7