SSTUAF32868AHLF IDT, Integrated Device Technology Inc, SSTUAF32868AHLF Datasheet

SSTUAF32868AHLF

Manufacturer Part Number

SSTUAF32868AHLF

Description

IC REGIST BUFF 25BIT DDR2 176BGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.SSTUAF32868AHLFT.pdf (21 pages)

Specifications of SSTUAF32868AHLF

Logic Type

1:1, 1:2 Configurable Registered Buffer

Supply Voltage

1.7 V ~ 1.9 V

Number Of Bits

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

176-BGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Company:

BOSTOCK HK LIMITED

Part Number:

SSTUAF32868AHLFT

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description

This 28-bit 1:2 configurable registered buffer is designed for

1.7V to 1.9V V

the JEDEC standard for SSTL_18, except the chip-select

gate-enable (CSGEN), control (C), and reset (RESET)

inputs, which are LVCMOS. All outputs are edge-controlled

circuits optimized for unterminated DIMM loads, and meet

SSTL_18 specifications, except the open-drain error

(QERR) output.

The ICSSSTUAF32868A operates from a differential clock

(CLK and CLK). Data are registered at the crossing of CLK

going high and CLK going low. The device supports

low-power standby operation. When RESET is low, the

differential input receivers are disabled, and undriven

(floating) data, clock, and reference voltage (Vref) inputs

are allowed. In addition, when RESET is low, all registers

are reset and all outputs are forced low except QERR. The

LVCMOS RESET and C inputs must always be held at a

valid logic high or low level. To ensure defined outputs from

the register before a stable clock has been supplied,

RESET must be held in the low state during power up. In

the DDR2 RDIMM application, RESET is specified to be

completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be ensured between

the two. When entering reset, the register will be cleared

and the data outputs will be driven low quickly, relative to

the time to disable the differential input receivers. However,

when coming out of reset, the register will become active

quickly, relative to the time to enable the differential input

receivers. As long as the data inputs are low, and the clock

is stable during the time from the low-to-high transition of

RESET until the input receivers are fully enabled, the

design of the ICSSSTUAF32868A must ensure that the

outputs will remain low, thus ensuring no glitches on the

output.

The ICSSSTUAF32868A includes a parity checking

function. Parity, which arrives one cycle after the data input

to which it applies, is checked on the PAR_IN input of the

device. The corresponding QERR output signal for the data

inputs is generated two clock cycles after the data, to which

the QERR signal applies, is registered. The

ICSSSTUAF32868A accepts a parity bit from the memory

controller on the parity bit (PAR_IN) input, compares it with

the data received on the DIMM-independent D-inputs

(D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12,

D17-D20, D22, D24-D28 when C = 1) and indicates

whether a parity error has occurred on the open-drain

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

operation. All inputs are compatible with

QERR pin (active low). The convention is even parity, i.e.,

valid parity is defined as an even number of ones across the

DIMM-independent data inputs combined with the parity

input bit. To calculate parity, all DIMM-independent D-inputs

must be tied to a known logic state. If an error occurs and

the QERR output is driven low, it stays latched low for a

minimum of two clock cycles or until RESET is driven low. If

two or more consecutive parity errors occur, the QERR

output is driven low and latched low for a clock duration

equal to the parity error duration or until RESET is driven

low. If a parity error occurs on the clock cycle before the

device enters the low-power (LPM) and the QERR output is

driven low, then it stays lateched low for the LPM duration

plus two clock cycles or until RESET is driven low. The

DIMM-dependent signals (DCKE0, DCKE1, DODT0,

DODT1, DCS0 and DCS1) are not included in the parity

check computation.

The C input controls the pinout configuration from

configuration (when high). The C input should not be

switched during normal operation. It should be hardwired to

a valid low or high level to configure the register in the

desired mode. The device also supports low-power active

operation by monitoring both system chip select (DCS0 and

DCS1) and CSGEN inputs and will gate the Qn outputs

from changing states when CSGEN, DCS0, and DCS1

inputs are high. If CSGEN, DCS0 orDCS1 input is low, the

Qn outputs will function normally. Also, if both DCS0 and

DCS1 inputs are high, the device will gate the QERR output

from changing states. If either DCS0 orDCS1 is low, the

QERR output will function normally. The RESET input has

priority over the DCS0 and DCS1 control and when driven

low will force the Qn outputs low, and the QERR output

high. If the chip-select control functionality is not desired,

then the CSGEN input can be hard-wired to ground, in

which case, the setup-time requirement for DCS0 and

DCS1 would be the same as for the other D data inputs. To

control the low-power mode with DCS0 and DCS1 only,

then the CSGEN input should be pulled up to Vdd through a

pullup resistor. The two V

connected together internally by approximately 150.

However, it is necessary to connect only one of the two

capacitor.

REF

CONFIDENTIAL

pins to the external V

pin should be terminated with a V

REF

ICSSSTUAF32868A

REF

pins (A1 and V1) are

ICSSSTUAF32868A

power supply. An unused

DATASHEET

REF

coupling

7094/15

Related parts for SSTUAF32868AHLF

SSTUAF32868AHLF Summary of contents

Page 1

CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V V operation. All inputs are compatible with DD the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and ...

Page 2

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage ...

Page 3

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity Logic Diagram M2 RESET L1 CLK M1 CLK D1-D5, D7, D9-D12, D17-D28 22 A5, AB5 V REF PAR_IN L3 K1 DCS0 L2 CSGEN J1 DCS1 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 D1-D5, ...

Page 4

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Block Diagram M2 RESET L1 CLK M1 CLK A5, AB5 V REF DCKE0, W1, Y1 DCKE1 2 DODT0, K1, J1 DODT1 2 N1 DCS0 L2 CSGEN P1 DCS1 OTHER ...

Page 5

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity Logic Diagram M2 RESET L1 CLK M1 CLK D1-D12, D17-D20, D22, 22 D24-D28 A5, AB5 V REF PAR_IN L3 N1 DCS0 L2 CSGEN P1 DCS1 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 D1-D12, ...

Page 6

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Pin Configuration 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ...

Page 7

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Pin Configuration GND GND GND (DCKE1 (DCKE0) Q6A E D9 GND GND ...

Page 8

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Function Table RESET DCS0 DCS1 ...

Page 9

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity and Standby Function Table RESET DCS0 DCS1 ...

Page 10

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...

Page 11

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Terminal Functions Terminal Name Characteristics GND REF CLK Differential Input CLK Differential Input C RESET CSGEN D1 - D28 DCS0, DCS1 DCKE0, DCKE1 DODT0, DODT1 PAR_IN Q1 - Q28 QCS0, ...

Page 12

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Operating Characteristics, T The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET ...

Page 13

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL ...

Page 14

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Timing Requirements Over Recommended Operating Free-Air Temperature Range Symbol Parameter f Clock Frequency CLOCK t Pulse Duration, CLK, CLK HIGH or LOW W 1,2 t Differential Inputs Active Time ACT 1,3 t Differential ...

Page 15

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET CSGEN DCS0 DCS1 CLK CLK t ACT Dn, DODTn, DCKEn Qn, QODTn, QCKEn PARIN QERR NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals ...

Page 16

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing NOTE: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the ...

Page 17

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET CSGEN DCS0 DCS1 CLK CLK Dn, DODTn, DCKEn Qn, QODTn, QCKEn PARIN QERR NOTE: 1.After RESET is switched from LOW to HIGH, all data and clock inputs signals must be ...

Page 18

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT CLK Out CLK Inputs CLK Test Point R 100 L = Test Point Simulation Load Circuit LVCMOS RESET Input t ...

Page 19

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT Out Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% 20% dv_f dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out ...

Page 20

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Ordering Information ICSSSTUAF XX XXX Family Device Type 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 XX X Package Shipping Carrier T Tape and Reel HLF Low Profile, Fine Pitch, Ball Grid Array - Lead-Free ...

Page 21

ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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