SSTUB32872AHLFT IDT, Integrated Device Technology Inc, SSTUB32872AHLFT Datasheet - Page 4

• Manufacturer Part Number: SSTUB32872AHLFT
• Description: IC REGIST BUFF 28BIT DDR2 96-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUB32872AHLFT

• Logic Type: Registered Buffer for DDR2
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Ball Assignment
1222F—3/13/07
Ungated inputs DCKE0, DCKE1,
Chip Select
gated inputs
Chip Select
inputs
Re-driven
outputs
Parity input
Parity error
output
Clock inputs
Miscellaneous
inputs
Signal Group
DODT0, DODT1
D0 ... D21
DCS0 , DCS1
Q0...Q21,
QCS 0-1,
QCKE0-1,
QODT0-1
PTYERR
CK, CK
RESET
VREF
PARIN
Signal Name
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Open drain
SSTL_18
1.8 V
LVCMOS
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
Type
one Chip Slect input is LOW.
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is LOW.
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
low when a valid address/command is present. The register
can be programmed to re-drive all D-inputs
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
odd parity across the D0...D20 inputs, at the rising edge of the
clock.
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by
an additional clock cycle for compatibility with final parity
out timing on the industry-standard DDR-II register with
parity (in JEDEC definition).
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET
also resets the PTYERR signal.
(internally tied together) are used for increased reliability.
Input parity is received on pin PARIN and should maintain
4
Description
ICSSSTUB32872A
Advance Information
when at least