SSTUB32S868DHLFT IDT, Integrated Device Technology Inc, SSTUB32S868DHLFT Datasheet
SSTUB32S868DHLFT
Specifications of SSTUB32S868DHLFT
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SSTUB32S868DHLFT Summary of contents
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Integrated Circuit Systems, Inc. 28-Bit Configurable Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533 and 667 Product Features: • 28-bit 1:2 registered buffer with ...
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(DCKE1 (DCKE0 Q6A (QCKE1A) F D10 Q8A QCKE0A G D11 Q10A H D12 Q12A J DCS1# QCS1A# K DCS0# QCS0A CSGEN M CK3 RESET# ...
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Q6A F D10 Q8A G D11 Q10A H D12 Q12A J D13 Q13A (DODT1) (QODT1A) K D14 Q14A (DODT0) (QODT0A CSG EN M CK# ...
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General Description This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. ...
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General Description (Continued) The ICSSSTUB32S868D includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. The corresponding QERR output signal for the data ...
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Ball Assignment Terminal name GND Ground V Power supply voltage DD V Input reference voltage REF CK Positive master clock input CK# Negative master clock input C Configuration control inputs - Register A or Register B Asynchronous reset input – ...
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Block Diagram M2 RST CK# A5, AB5 V REF D1, C1 DCKE0, 2 DCKE1 N1, P1 DODT0, 2 DODT1 K1 DCS0# L2 CSGEN J1 DCS1 (D2-D5, D7, D9-D12, D17-D28) Register A configuration with C= O; ...
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Parity Logic Diagram M2 RST CK# D1-D5, D1-D5, D7, D7, D9-D12, D9-D12, 22 D17-D28 D17-D28 A5, AB5 V REF L3 PAR_IN K1 DCS0# L2 CSGEN J1 DCS1# Register A configuration with C= O; (positive logic) 08/14/06 D ...
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Block Diagram M2 RST CK# A5, AB5 V REF W1, Y1 DCKE0, 2 DCKE1 K1, J1 DODT0, 2 DODT1 N1 DCS0# L2 CSGEN P1 DCS1 Other Channels (D2-D12, D17-D20, D22, D24-D28) Register B ...
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Parity Logic Diagram M2 RST CK# D1-D12, D1-D12, D17-D20, D17-D20, D22, D22, 22 D24-D28 D24-D28 A5, AB5 V REF L3 PAR_IN N1 DCS0# L2 CSGEN P1 DCS1# Register B configuration with C= 1; (positive logic) 08/14/06 D ...
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Register Timing RST# CSGEN DCS0# DCS1# CK CK# t act Dn, DODTn, DCKEn Qn, QODTn, QCKEn PAR_IN QERR# † After RESET# is switched from low to high, all data and PAR_IN input signals must be set and held low for ...
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Register Timing RST# CSGEN DCS0# DCS1# CK CK# Dn, DODTn, DCKEn Qn, QODTn, QCKEn PAR_IN QERR# Unknown input event † If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the ...
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Register Timing RST# CSGEN DCS0# DCS1# CK CK# Dn, DODTn, DCKEn Qn, QODTn, QCKEn PAR_IN QERR# † After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) ...
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Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...
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Electrical Characteristics - 70° 2.5 +/-0.2V DDQ SYMBOL PARAMETERS V Output HIGH voltage Output LOW voltage All Inputs ...
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Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) Symbol f Clock frequency clock t Pulse duration, CK, CK# HIGH or LOW W t Differential inputs active time (See Notes 1 and 2) ACT t Differential inputs inactive ...
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CK Inputs Test Point R = 100Ω L Test Point VCMOS RST Inp act I DD (see 10% Note 2) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES t w Inpu t V ...
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Output slew rate measurement information (V All input pulses are supplied by generators having the following characteristics: PRR input slew rate = 1 V/ns ± 20%, unless otherwise specified. o (1) C includes probe and jig ...
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Error output load circuit and voltage measurement information (V All input pulses are supplied by generators having the following characteristics: PRR input slew rate = 1 V/ns ± 20%, unless otherwise specified. o (1) C includes ...
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A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 15.00 Bsc 6.00 Bsc 1.00/1.20 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC ...