IDT74SSTUA32866BFG IDT, Integrated Device Technology Inc, IDT74SSTUA32866BFG Datasheet

IDT74SSTUA32866BFG

Manufacturer Part Number

IDT74SSTUA32866BFG

Description

IC BUFFER 1.8V CONFIG 96-BGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT74SSTUA32866BFG8.pdf (19 pages)

Specifications of IDT74SSTUA32866BFG

Logic Type

1:2 Configurable Registered Buffer

Supply Voltage

1.7 V ~ 1.9 V

Number Of Bits

25, 14

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

96-LFBGA

Logic Family

SSTU

Logical Function

Registered Buffer

Number Of Elements

Number Of Inputs

Number Of Outputs

High Level Output Current

-8mA

Low Level Output Current

8mA

Propagation Delay Time

2.4ns

Operating Supply Voltage (typ)

1.8V

Operating Supply Voltage (max)

1.9V

Operating Supply Voltage (min)

1.7V

Clock-edge Trigger Type

Posit/Negat-Edge

Polarity

Non-Inverting

Technology

CMOS

Frequency (max)

410(Min)MHz

Mounting

Surface Mount

Pin Count

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74SSTUA32866BFG

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

IDT74SSTUA32866BFG

Manufacturer:

IDT

Quantity:

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUA32866BFG

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUA32866BFG

Manufacturer:

Quantity:

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUA32866BFG8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Current page: 1 of 19
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FEATURES:

• 1.8V Operation

• SSTL_18 style clock and data inputs

• Differential CLK input

• Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer

• Control inputs compatible with LVCMOS levels

• Flow-through architecture for optimum PCB design

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

• Checks parity on data inputs

• Maximum operating frequency: 410MHz

• Optimized for DDR2 - 400 / 533 / 667 (PC2 - 3200 / 4300 / 5300)

• Available in 96-pin LFBGA package

APPLICATIONS:

• Along with CSPUA877 DDR2 PLL, provides complete solution for

DESCRIPTION:

1.7V to 1.9V V

per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinout

configuration, two devices per DIMM are required to drive eighteen

SDRAM loads. All inputs are SSTL_18, except reset (RESET) and control

(Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits

optimized for unterminated DIMM loads, and meet SSTL_18 specifications,

except the open-drain error (QERR) output.

Data are registered at the crossing of CLK going high and CLK going low.

Parity is checked on the parity bit (PAR_IN) input which arrives one cycle

after the input data to which it applies. The QERR output is open drain.

configuration, the partial-parity-out (PPO) and QERR signals are produced

two clock cycles after the corresponding data output.

COMMERCIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74SSTUA32866

1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

JEDEC R/C E, F, G, H, and J

DDR2 DIMMs

This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for

The SSTUA32866 operates from a differential clock (CLK and CLK).

When used as a single device, the C0 and C1 inputs are tied low. In this

machine model (C = 200pF, R = 0)

2005 Integrated Device Technology, Inc.

operation. In the 1:1 pinout configuration, only one device

1.8V CONFIGURABLE

BUFFER WITH ADDRESS-

PARITY TEST

C0 input of the second register is tied high. The C1 input of both registers

are tied high. The QERR output of the first SSTUA32866 is left floating and

the valid error information is latched on the QERR output of the second

SSTUA32866.

for two clock cycles or until RESET is driven low. The DIMM-dependent

signals (DODT, DCKE, DCS, and CSR) are not included in the parity check.

The C1 input controls the pinout configurationfrom 25-bit 1:1 (when low) to

14-bit 1:2 (when high). C0 and C1 should not be switched during normal

operation. They should be hard-wired to a valid low or high level to

configure the register in the desired mode. In the 25-bit 1:1 pinout

configuration, the A6, D6, and H6 terminals are driven low and should not

be used.

the differential input recievers are disabled, and undriven (floating) data,

clock, and reference voltage (V

RESET is low, all registers are reset and all outputs except QERR are forced

low. The LVCMOS RESET and Cn inputs always must be held at a valid

logic high or low level.

connect one of the two V

unused V

system chip select (DCS and CSR) inputs and will gate the Qn and PPO

outputs from changing states when both DCS and CSR inputs are high. If

either DCS or CSR input is low, the Qn and PPO outputs will function

normally. Also, if the internal low power signal (LPS1) is high, the device

will gate the QERR output from changing states. If LPS1 is low, the QERR

output will function normally. The RESET input has priority over the DCS

and CSR control and when driven low will force the Qn and PPO outputs

low, and the QERR output high. If the DCS control functionality is not desired,

then the CSR input can be hard-wired to ground, in which case the setup-

time requirement for DCS would be the same as for the other D data inputs.

To control the low-power mode with DCS only, then the CSR input should

be pulled up to V

supplied, RESET must be held in the low state during power up.

When used in pairs, the C0 input of the first register is tied low and the

If an error occurs and the QERR output is driven low, it stays latched low

The CO input controls the pinout configuration of the 1:2 pinout from

The device supports low-power standby operation. When RESET is low,

There are two V

The device also supports low-power active operation by monitoring both

To ensure defined outputs from the register before a stable clock has been

REF

pin should be terminated with a V

REF

through a pullup resistor.

pins (A3 and T3). However, it is necessary to only

REF

COMMERCIAL TEMPERATURE RANGE

pins to the external V

REF

) inputs are allowed. In addition, when

IDT74SSTUA32866

REF

coupling capacitor.

REF

JUNE 2005

power supply. An

DSC 6382/9

Related parts for IDT74SSTUA32866BFG

IDT74SSTUA32866BFG Summary of contents

Page 1

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES: • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer • Control inputs compatible with LVCMOS levels ...

Page 2

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTIONAL BLOCK DIAGRAM (1: CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS (D3, D5, D6, D8-D14) COMMERCIAL TEMPERATURE RANGE 1D C1 ...

Page 3

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTIONAL BLOCK DIAGRAM (1: CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS (D2-D6, D8-D10, D12-D13) COMMERCIAL TEMPERATURE RANGE ...

Page 4

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST PIN CONFIGURATION (TYPE A) 6 Q2B Q3B QCKEB QODTB 5 QCKEA Q2A Q3A QODTA 4 V GND V GND GND V GND DD REF 2 PPO DNU DNU ...

Page 5

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTIONAL BLOCK DIAGRAM (1:1) RESET CLK1 CLK1 V REF DCKE DODT DCS CSR OTHER CHANNELS (D3, D5, D6, D8-D25) COMMERCIAL TEMPERATURE RANGE ...

Page 6

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST PIN CONFIGURATION DNU 6 Q15 Q16 DNU 5 QCKE Q2 Q3 QODT 4 V GND V GND GND V GND DD REF 2 PPO D15 D16 QERR 1 ...

Page 7

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTION TABLE (EACH FLIP-FLOP) (1) RESET DCS CSR ...

Page 8

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST LOGIC DIAGRAM (1:1) G2 RESET H1 CLK J1 CLK (Internal Node D3 D6 D25 A3 REF PAR_IN G6 C0 Counter ...

Page 9

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST LOGIC DIAGRAM (1:2) G2 RESET H1 CLK J1 CLK (Internal Node D3 D6 D14 D A3 REF PAR_IN G6 ...

Page 10

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply Voltage Range DD (2,3) V Input Voltage Range I (2,3) V Output Voltage Range O I Input Clamp Current V < ...

Page 11

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST OPERATING CHARACTERISTICS, T Symbol Parameter V Supply Voltage DD V Reference Voltage REF V Termination Voltage TT V Input Voltage High-Level Input Voltage Low-Level Input Voltage ...

Page 12

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE Symbol Parameter f Clock Frequency CLOCK tw Pulse Duration, CLK, CLK HIGH or LOW ACT (1,2) t Differential Inputs Active Time INACT (1,3) t ...

Page 13

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST REGISTER TIMING RESET DCS CSR CLK CLK D1 - D25 Q1 - Q25 PAR_IN PPO QERR Timing Diagram for SSTUA32866 Used as a Single Device ...

Page 14

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST REGISTER TIMING RESET DCS CSR CLK CLK D1 - D14 Q1 - Q14 PAR_IN PPO QERR (not used) Timing Diagram for the First SSTUA32866 (1:2 Register-A Configuration) Device Used in a Pair; ...

Page 15

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST REGISTER TIMING RESET DCS CSR CLK CLK D1 - D14 Q1 - Q14 (1) PAR_IN PPO (not used) QERR Timing Diagram for the First SSTUA32866 (1:2 Register-B Configuration) Device Used in a ...

Page 16

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TEST CIRCUITS AND WAVEFORMS (V CLK Inputs LVCMOS RESET Input t INACT I DD 10% Voltage and Current Waveforms Inputs Active and Inactive Times t W Input V ICR ...

Page 17

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TEST CIRCUITS AND WAVEFORMS (V Output Output NOTES includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz ...

Page 18

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TEST CIRCUITS AND WAVEFORMS (V DUT Out Load Circuit: QERR QERR QERR Output QERR QERR DUT Out Load Circuit: Partial-Parity-Out Load Circuit ...

Page 19

IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST ORDERING INFORMATION XX XXX IDT SSTUA32 Temp. Range Device Type XX Package BFG Low Profile, Fine Pitch, Ball Grid Array - Green 866 1.8V Configurable Registered Buffer with Address-Parity Test 74 0°C ...

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