IS43DR32800A-5BBL-TR ISSI, IS43DR32800A-5BBL-TR Datasheet - Page 30

• Manufacturer Part Number: IS43DR32800A-5BBL-TR
• Description: DRAM 256M (8Mx32) 200MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-5BBL-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

IS43DR32800A, IS43/46DR32801A
Mode Register (MR)
The mode register stores the data for controlling the various operating modes of the DDR2 SDRAM. It controls
CAS latency, burst length, burst sequence, DLL reset, WR and power down exit time to make DDR2 SDRAM useful
for various applications. The default value of the mode register is not defined, therefore the mode register must be
programmed during initialization for proper operation. The mode register is written by asserting LOW on CS, RAS,
CAS, WE, BA0 and BA1, while controlling the state of address pins A0 - A12. The DDR2 SDRAM should be in all
bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command
cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as all banks are in
the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined
by A0 - A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst
address sequence type is defined by A3, CAS latency is defined by A4 - A6. The DDR2 does not support half clock
latency mode. A7 is a mode bit and must be set to LOW for normal MRS operation. A8 is used for DLL reset. Write
recovery time WR is defined by A9 - A11. Active power down exit time is defined by A12. Refer to the table for specific
codes.
DDR2 SDRAM mode register set (MRS)
Notes:
1. For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock
2. Speed option determined. Refer to Key Timing Parameter table.
30
Address
A12
Field
cycles is calculated by dividing tWR (ns) by tCK (ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU
stands for round up). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
Latency
Register
Length
Burst
Mode
CAS
PD
DLL
TM
WR
BT
0
0
A12
A11
A8
A6
A3
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
A10
A5
Active power down exit time
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Slow exit(use tXARDS)
Fast exit (use tXARD)
DLL Reset
Burst Type
Sequential
Interleave
Yes
A9
No
A4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WR(cycles)
Reserved
Reserved
Reserved
2
3
4
5
6
*1
CAS Latency
Reserved
Reserved
Reserved
Reserved
Integrated Silicon Solution, Inc. — www.issi.com
3
4*
5
6
*2
*2
*2
2
A7
A2
0
1
0
0
A1
1
1
t
Reserved
CK
Normal
Mode
(ns) for speed option
A0
-5B
0
1
5
5
5
5
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BL
-37C
4
8
3.75
3.75
3.75
5
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2
09/08/2010
Rev. 00E