IS43DR32800A-5BBL-TR ISSI, IS43DR32800A-5BBL-TR Datasheet - Page 13

• Manufacturer Part Number: IS43DR32800A-5BBL-TR
• Description: DRAM 256M (8Mx32) 200MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-5BBL-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

IS43DR32800A, IS43/46DR32801A
IDD Specifications & Test Conditions (continued)
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and DQS. IDD values must be met with all combinations of EMR(1) bits 10 and 11.
5. Definitions for IDD
LOW = Vin ≤ VILAC(max)
HIGH = Vin ≥ VIHAC(min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at VREF = VDDQ/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs
changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
Symbol
IDD4R
IDD5B
IDD6
IDD7
Conditions
Operating burst read current; All banks open, Continuous burst reads,
IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
50% of Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Burst refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval;
CKE is HIGH, CS is HIGH between valid commands;
Other control and 50% of address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self refresh current;
CK and CK at 0 V; CKE ≤ 0.2 V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK(IDD);
CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs;
Reduced Page
(8K)
Standard Page
(4K)
DDR2-
533C
-37C
240
170
265
450
6
DDR2-
400B
180
150
245
430
-5B
6
Units
mA
mA
mA
mA
13