IS43DR32800A-5BBL-TR ISSI, IS43DR32800A-5BBL-TR Datasheet - Page 22

• Manufacturer Part Number: IS43DR32800A-5BBL-TR
• Description: DRAM 256M (8Mx32) 200MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-5BBL-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet
tIS(base) and tIH(base) value to the DtIS and DtIH derating value respectively. Example: tIS (total setup time) =
tIS(base) + DtIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and
the first crossing of Vih(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal
slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is
later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line
to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and
the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(dc) level is used for derating value.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/
IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach
VIH/IL(ac).
For slew rates in between the values listed in the "Input Setup and Hold Time Derating" table, the derating values may
obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
IS43DR32800A, IS43/46DR32801A
9. Input Setup and Hold Time Derating (tIS, tIH)
22
Command/
Slew rate
Address
(V/ns)
0.25
0.15
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
4.0
3.5
2.5
2.0
1.5
3
tIS, tIH Derating Values for DDR2-400, DDR2-533
-1450
-110
-175
-285
-350
-525
-800
DtIS
187
179
167
150
125
-11
-25
-43
-67
83
0
2.0 V/ns
CK, /CK Differential Slew Rate
-1125
-125
-188
-292
-375
-500
-708
DtIH
-14
-31
-54
-83
94
89
83
75
45
21
0
-1420
-145
-255
-320
-495
-770
DtIS
217
209
197
180
155
113
-13
-37
-80
30
19
5
1.5 V/ns
Integrated Silicon Solution, Inc. — www.issi.com
-1095
-158
-262
-345
-470
-678
DtIH
124
119
113
105
-24
-53
-95
75
51
30
16
-1
-1390
-115
-225
-290
-465
-740
DtIS
247
239
227
210
185
143
-50
60
49
35
17
-7
1.0 V/ns
-1065
-128
-232
-315
-440
-648
DtIH
154
149
143
135
105
-23
-65
81
60
46
29
6
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
09/08/2010
Rev. 00E