SSTUA32S865ET/G;55 NXP Semiconductors, SSTUA32S865ET/G;55 Datasheet
SSTUA32S865ET/G;55
Specifications of SSTUA32S865ET/G;55
SSTUA32S865ET/G
SSTUA32S865ET/G
Related parts for SSTUA32S865ET/G;55
SSTUA32S865ET/G;55 Summary of contents
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SSTUA32S865 1.8 V 28-bit registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 16 March 2007 1. General description The SSTUA32S865 is a 1.8 V 28-bit register specifically designed for use on ...
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... NXP Semiconductors 3. Applications I 400 MT/s to 667 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs I DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality 4. Ordering information Table 1. Ordering information Type number Solder process SSTUA32S865ET/G Pb-free (SnAgCu solder ball compound) SSTUA32S865ET SnPb solder ball compound ...
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... NXP Semiconductors 5. Functional diagram VREF PARIN D0 D21 DCS0 CSGATEEN DCS1 DCKE0, 2 DCKE1 DODT0, 2 DODT1 RESET CK CK Fig 1. Functional diagram of SSTUA32S865 SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity (CS ACTIVE) PARITY D Q GENERATOR AND 22 R CHECKER Rev. 02 — 16 March 2007 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration for TFBGA160 SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity SSTUA32S865ET/G SSTUA32S865ET ball A1 index area 002aab387 Transparent top view Rev. 02 — 16 March 2007 SSTUA32S865 11 © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors VREF n.c. PARIN n. D11 D9 F D18 D12 G CSGATEEN D15 H CK DCS0 J CK DCS1 K RESET D14 L D0 D10 M D17 D16 N D19 D21 P D13 D20 R DODT1 DODT0 T DCKE0 DCKE1 MCL U VREF MCL MCL V 160-ball grid; top view. An empty cell indicates no ball is populated at that grid point. ...
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... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin Ungated inputs DCKE0, DCKE1 U1, U2 DODT0, DODT1 T2, T1 Chip Select gated inputs D0 to D21 M1, B1, B2, C1, C2, D2, D1, E1, E2, F2, M2, F1, G2, R1, L2, H2, N2, N1, G1, P1, R2, P2 Chip Select inputs DCS0, DCS1 J2, K2 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Clock inputs CK, CK J1, K1 Miscellaneous inputs MCL U3, V2, V3 MCH U5, V5 RESET L1 VREF A1, V1 VDDL D4, E4, E6, F4, G4, H4, K4, K5, N4, N5, P5, P6, R5, R6 VDDR E7, F8, F9, G8, G9, J8, J9, L8, L9, N8, N9, P7, P8 GND D5, D8, D9, E5, E8, E9, F5, ...
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... NXP Semiconductors 7. Functional description 7.1 Function table Table 3. Function table (each flip-flop) RESET DCS0 DCS1 floating floating [ the previous state of the associated output. 0 Table 4. Parity and standby function table RESET DCS0 DCS1 floating X or floating [1] PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated correctly ...
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... NXP Semiconductors [2] This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is ‘don’t care’ for PTYERR. [3] PTYERR is the previous state of output PTYERR. ...
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... NXP Semiconductors 7.3 Functional differences to SSTU32864 The SSTUA32S865 for its basic register functionality, signal definition and performance is based upon the industry-standard SSTU32864, but provides key operational features which differ (at least in part) from the industry-standard register in the following aspects: 7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN) ...
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... NXP Semiconductors RESET DCSn ACT ( PARIN PTYERR HIGH, LOW, or Don't care (1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum time avoid false error. ACT(max) Fig 4. RESET switches from LOW to HIGH ...
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... NXP Semiconductors RESET DCSn PDM Qn PARIN PTYERR Unknown input event Fig 5. RESET being held HIGH SSTUA32S865_2 Product data sheet PDMSS Output signal is dependent on the prior unknown event Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity PHL PLH ...
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... NXP Semiconductors RESET DCSn (1) CK ( (1) PARIN PTYERR (1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of t Fig 6. RESET switches from HIGH to LOW SSTUA32S865_2 Product data sheet ...
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... NXP Semiconductors PARIN CLOCK (1) This function holds the error for two cycles. For details, see switches from LOW to HIGH”. Fig 7. Parity logic diagram SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity Section 7 “Functional description” Rev. 02 — 16 March 2007 ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O I continuous current through ...
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... NXP Semiconductors 10. Characteristics Table 8. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per MHz C input capacitance i SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity ...
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... NXP Semiconductors Table 9. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t set-up time su t hold time h [1] This parameter is not necessarily production tested. ...
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... NXP Semiconductors 11. Test information 11.1 Test circuit All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) unless otherwise specified. The outputs are measured one at a time with one transition per measurement. CK inputs (1) C Fig 8. Load circuit (1) I Fig 9. Voltage and current waveforms ...
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... NXP Semiconductors Fig 11. Voltage waveforms; setup and hold times Fig 12. Voltage waveforms; propagation delay times (clock to output) Fig 13. Voltage waveforms; propagation delay times (reset to output) SSTUA32S865_2 Product data sheet input V ref V = 600 mV 0.5V . ref 250 mV (AC voltage levels) for differential inputs. V ...
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... NXP Semiconductors 11.2 Output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 14. Load circuit, HIGH-to-LOW slew measurement Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) C Fig 16. Load circuit, LOW-to-HIGH slew measurement Fig 17 ...
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... NXP Semiconductors 11.3 Error output load circuit and voltage measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 18. Load circuit, error output measurements Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect ...
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... NXP Semiconductors Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUA32S865_2 Product data sheet timing V ICR inputs t LH output waveform 2 clock inputs Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity V V i(p-p) ICR 002aaa503 © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors 12. Package outline TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 0.8 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.35 0.85 0.45 mm 1.2 0.25 0.75 0.35 OUTLINE VERSION IEC SOT802 Fig 22. Package outline SOT802-1 (TFBGA160) ...
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... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . SSTUA32S865_2 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
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... Release date SSTUA32S865_2 20070316 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Figure 6 “RESET switches from HIGH to “t ” ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 8 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Functional information . . . . . . . . . . . . . . . . . . . 9 7.3 Functional differences to SSTU32864 . . . . . . 10 7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN) ...