IS43DR32800A-5BBL ISSI, IS43DR32800A-5BBL Datasheet - Page 3

• Manufacturer Part Number: IS43DR32800A-5BBL
• Description: DRAM 256M (8Mx32) 200MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-5BBL

• Product Category: DRAM
• Rohs: yes
• Data Bus Width: 32 bit
• Package / Case: WBGA-126
• Memory Size: 256 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 0.6 ns
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 210 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 162

IS43DR32800A, IS43/46DR32801A
PIN DESCRIPTION TABLE
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
Symbol
CK, CK
CKE
CS
ODT
RAS, CAS, WE
(DM0-DM3)
BA0 - BA1
A0 - A12
Type
Input
Input
Input
Input
Input
Input
Input
Input
Function
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of
crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE LOW provides Precharge
Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After VREF has become
stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must be maintained to this input. CKE must be maintained HIGH throughout read and
write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during
power-down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external Rank selection on systems with multiple Ranks. CS is considered part of the
command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal
to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DQM
signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. The function of DM is enabled by EMRS command
to EMR(1).
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines if the mode
register or one of the extended mode registers is to be accessed during a MRS or
EMRS command cycle.
Address Inputs: Provide the row address for Active commands and the column
address and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 -
BA1. The address inputs also provide the op-code during MRS or EMRS commands.
Standard Page option only: A12 is not used for addressing, but is necessary as an
input for the setting of the Mode Register (MRS) and Extended Mode Registers
(EMR). If not implemented for MRS/EMR, A12 can be left connected to Vss. It must
not be left floating.
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