SSTUM32866EC/S,518 NXP Semiconductors, SSTUM32866EC/S,518 Datasheet
SSTUM32866EC/S,518
Specifications of SSTUM32866EC/S,518
SSTUM32866EC/S-T
SSTUM32866EC/S-T
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SSTUM32866EC/S,518 Summary of contents
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SSTUM32866 1.8 V 25-bit 14-bit configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 29 June 2007 1. General description The SSTUM32866 is a 1.8 V configurable register specifically designed ...
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... NXP Semiconductors 3. Applications I 400 MT/s to 800 MT/s and higher DDR2 registered DIMMs desiring parity checking functionality 4. Ordering information Table 1. Ordering information Type number Solder process SSTUM32866EC/G Pb-free (SnAgCu solder ball compound) SSTUM32866EC/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. ...
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... NXP Semiconductors 5. Functional diagram (1) Disabled configuration. Fig 1. Functional diagram of SSTUM32866 Register A configuration with and SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity RESET CK CK VREF DCKE DODT DCS CSR other channels (D3, D5, D6 D14 (positive logic) Rev. 01 — ...
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... NXP Semiconductors RESET CK CK D2, D3, D5, D6 D14 VREF C1 PAR_IN C0 Fig 2. Parity logic diagram for Register A configuration (positive logic SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity LPS0 (internal node CLK R D2, D3, D5, D6 D14 PARITY CHECK CLK ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for LFBGA96 Fig 4. Ball mapping register ( SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity SSTUM32866EC/G SSTUM32866EC/S ball A1 index area 002aad084 Transparent top view DCKE PPO VREF V DD ...
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... NXP Semiconductors Fig 5. Ball mapping Register A ( Fig 6. Ball mapping Register B ( SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity DCKE PPO VREF DNU GND GND C D3 DNU DODT QERR GND GND n.c. GND GND G PAR_IN RESET DCS ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3 A4, C3, C4, E3, E4, DD G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 VREF A3 RESET G2 CSR J2 DCS H2 [ D25 [2] DODT [2] DCKE PAR_IN G1 [ Q25, Q1A to Q14A, Q1B to Q14B PPO A2 [2] ...
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... NXP Semiconductors [3] Data outputs = Q2, Q3, Q5, Q6 Q25 when and Data outputs = Q2, Q3, Q5, Q6 Q14 when and Data outputs = Q10, Q12, Q13 when and Functional description The SSTUM32866 is a 25-bit 14-bit configurable registered buffer with parity, designed for 1 2 All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS ...
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... NXP Semiconductors The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn and PPO outputs will function normally ...
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... NXP Semiconductors Table 5. Parity and standby function table L = LOW voltage level HIGH voltage level don’t care; RESET DCS CSR floating X or floating X or floating X or floating [1] PPO is the previous state of output PPO; QERR 0 [2] Data inputs = D2, D3, D5, D6 D25 when and ...
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... NXP Semiconductors 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter V supply voltage DD V reference voltage ref V termination voltage T V input voltage HIGH-level input voltage IH(AC LOW-level input voltage IL(AC HIGH-level input voltage IH(DC LOW-level input voltage IL(DC) V HIGH-level input voltage ...
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... NXP Semiconductors 10. Characteristics Table 8. Characteristics At recommended operating conditions (see Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current per DDD MHz C input capacitance i Z output impedance o [1] Instantaneous is defined as within < following the output data transition edge. ...
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... NXP Semiconductors Table 9. Timing requirements At recommended operating conditions (see Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t setup time su t hold time h [1] This parameter is not necessarily production tested. [2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t HIGH ...
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... NXP Semiconductors 10.1 Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUM32866 used as a single device SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity PPO QERR Rev. 01 — 29 June 2007 SSTUM32866 ...
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... NXP Semiconductors RESET DCS CSR D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUM32866 ( Register A configuration) device used in pair SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity PPO QERR Rev. 01 — 29 June 2007 ...
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... NXP Semiconductors RESET DCS CSR D14 Q14 (1) PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUM32866 device. Fig 9. Timing diagram for the second SSTUM32866 ( Register B configuration) device used in pair SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity ...
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... NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time with one transition per measurement. CK inputs (1) C Fig 10. Load circuit, data output measurements (1) I Fig 11. Voltage and current waveforms ...
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... NXP Semiconductors Fig 13. Voltage waveforms; setup and hold times Fig 14. Voltage waveforms; propagation delay times (clock to output) Fig 15. Voltage waveforms; propagation delay times (reset to output) SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity input V ref V = 600 mV. ...
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... NXP Semiconductors 11.2 Data output slew rate measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 16. Load circuit, HIGH-to-LOW slew measurement Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) C Fig 18. Load circuit, LOW-to-HIGH slew measurement Fig 19 ...
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... NXP Semiconductors 11.3 Error output load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 20. Load circuit, error output measurements Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to Fig 22 ...
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... NXP Semiconductors Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to 11.4 Partial parity out load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 24. Partial parity out load circuit Fig 25. Partial parity out voltage waveforms ...
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... NXP Semiconductors Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity LVCMOS RESET output and t are the same PLH PHL 250 mV (AC voltage levels) for differential inputs. V ...
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... NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.41 1.2 0.51 mm 1.5 0.31 0.9 0.41 OUTLINE VERSION IEC SOT536-1 Fig 27 ...
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... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 14. Acronym CMOS DDR DIMM DUT LVCMOS PPO PRR RDIMM SSTL 15. Revision history Table 15 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . . 8 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Limiting values Recommended operating conditions Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 14 11 Test information ...