SSTUB32866EC/G,518 NXP Semiconductors, SSTUB32866EC/G,518 Datasheet
SSTUB32866EC/G,518
Specifications of SSTUB32866EC/G,518
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SSTUB32866EC/G-T
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SSTUB32866EC/G,518 Summary of contents
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SSTUB32866 1.8 V 25-bit 14-bit configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 15 April 2010 1. General description The SSTUB32866 is a 1.8 V configurable register specifically designed ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Solder process SSTUB32866EC/G Pb-free (SnAgCu solder ball compound) SSTUB32866EC/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUB32866EC/G SSTUB32866EC/S SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity ...
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... NXP Semiconductors 5. Functional diagram (1) Disabled configuration. Fig 1. SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity RESET CK CK VREF DCKE DODT DCS CSR other channels (D3, D5, D6 D14) Functional diagram of SSTUB32866 Register A configuration with and (positive logic) All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors RESET CK CK D2, D3, D5, D6 D14 VREF C1 PAR_IN C0 Fig 2. Parity logic diagram for Register A configuration (positive logic SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity LPS0 (internal node CLK R D2, D3, D5, D6 D14 PARITY CHECK CLK R R CLK ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Fig 4. SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity ball A1 index area Pin configuration for LFBGA96 DCKE PPO B D2 D15 C D3 D16 D DODT QERR E D5 D17 F D6 D18 G PAR_IN RESET H CK ...
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... NXP Semiconductors Fig 5. Fig 6. SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity DCKE PPO B D2 DNU C D3 DNU D DODT QERR n.c. G PAR_IN RESET H CK DCS J CK CSR K D8 DNU L D9 DNU M D10 DNU N D11 DNU P D12 DNU ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3 A4, C3, C4, E3, E4, DD G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 VREF A3 RESET G2 CSR J2 DCS H2 [ D25 [2] DODT [2] DCKE PAR_IN G1 [ Q25, Q2A to Q14A, Q1B to Q14B PPO A2 [2] ...
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... NXP Semiconductors [3] Data outputs = Q2, Q3, Q5, Q6 Q25 when and Data outputs = Q2, Q3, Q5, Q6 Q14 when and Data outputs = Q10, Q12, Q13 when and Functional description The SSTUB32866 is a 25-bit 14-bit configurable registered buffer with parity, designed for 1 2 All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS ...
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... NXP Semiconductors The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn and PPO outputs will function normally ...
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... NXP Semiconductors Table 5. Parity and standby function table L = LOW voltage level HIGH voltage level don’t care; RESET DCS CSR floating X or floating X or floating X or floating [1] PPO is the previous state of output PPO; QERR 0 [2] Data inputs = D2, D3, D5, D6 D25 when and ...
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... NXP Semiconductors 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter V supply voltage DD V reference voltage ref V termination voltage T V input voltage HIGH-level input voltage IH(AC LOW-level input voltage IL(AC HIGH-level input voltage IH(DC LOW-level input voltage IL(DC) V HIGH-level input voltage ...
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... NXP Semiconductors 10. Characteristics Table 8. Characteristics At recommended operating conditions (see Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per MHz C input capacitance i Input RESET V LOW-level input voltage IL V HIGH-level input voltage ...
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... NXP Semiconductors Table 9. Timing requirements At recommended operating conditions (see Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t set-up time su t hold time h [1] This parameter is not necessarily production tested. [2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t HIGH ...
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... NXP Semiconductors 10.1 Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUB32866 used as a single device SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity PPO CK to QERR All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors RESET DCS CSR D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUB32866 ( Register A configuration) device used in pair SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity PPO QERR All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors RESET DCS CSR D14 Q1 to Q14 (1) PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUB32866 device. Fig 9. Timing diagram for the second SSTUB32866 ( Register B configuration) device used in pair SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity ...
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... NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit = 1.8 V ± 0 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z The outputs are measured one at a time with one transition per measurement. CK inputs (1) C Fig 10 ...
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... NXP Semiconductors Fig 13. Voltage waveforms; set-up and hold times Fig 14. Voltage waveforms; propagation delay times (clock to output) Fig 15. Voltage waveforms; propagation delay times (reset to output) SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity input V ref V = 600 mV 0.5V . ref ...
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... NXP Semiconductors 11.2 Data output slew rate measurement information = 1.8 V ± 0 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z (1) C Fig 16. Load circuit, HIGH-to-LOW slew measurement Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) C Fig 18. Load circuit, LOW-to-HIGH slew measurement Fig 19 ...
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... NXP Semiconductors 11.3 Error output load circuit and voltage measurement information = 1.8 V ± 0 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z (1) C Fig 20. Load circuit, error output measurements Fig 21. Voltage waveforms, open-drain output LOW to HIGH transition time with respect Fig 22 ...
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... NXP Semiconductors Fig 23. Voltage waveforms, open-drain output LOW to HIGH transition time with respect 11.4 Partial parity out load circuit and voltage measurement information = 1.8 V ± 0 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z (1) C Fig 24. Partial parity out load circuit Fig 25. Partial parity out voltage waveforms ...
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... NXP Semiconductors Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity LVCMOS RESET output and t are the same PLH PHL 250 mV (AC voltage levels) for differential inputs. V ...
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... NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.41 1.2 0.51 mm 1.5 0.31 0.9 0.41 OUTLINE VERSION IEC SOT536-1 Fig 27 ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 14. Acronym CMOS DDR DIMM LVCMOS PPO PRR RDIMM SSTL SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity ...
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... NXP Semiconductors 15. Revision history Table 15. Revision history Document ID Release date SSTUB32866_4 20100415 • Modifications: Section 1 “General • Table 8 SSTUB32866_3 20070423 SSTUB32866_2 20061009 SSTUB32866_1 20060518 SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity Data sheet status Product data sheet description” ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . . 8 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Limiting values Recommended operating conditions Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 10 ...