IDT74SSTUBF32868ABKG IDT, Integrated Device Technology Inc, IDT74SSTUBF32868ABKG Datasheet
IDT74SSTUBF32868ABKG
Specifications of IDT74SSTUBF32868ABKG
800-1696
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IDT74SSTUBF32868ABKG Summary of contents
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CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V V operation. All inputs are compatible with DD the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity Logic Diagram M2 RESET L1 CLK M1 CLK D1-D5, D7, D9-D12, D17-D28 22 A5, AB5 V REF PAR_IN L3 K1 DCS0 L2 CSGEN J1 DCS1 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 D1-D5, ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Block Diagram M2 RESET L1 CLK M1 CLK A5, AB5 V REF DCKE0, W1, Y1 DCKE1 2 DODT0, K1, J1 DODT1 2 N1 DCS0 L2 CSGEN P1 DCS1 OTHER ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity Logic Diagram M2 RESET L1 CLK M1 CLK D1-D12, D17-D20, D22, 22 D24-D28 A5, AB5 V REF PAR_IN L3 N1 DCS0 L2 CSGEN P1 DCS1 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 D1-D12, ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Pin Configuration 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Pin Configuration GND GND GND (DCKE1 (DCKE0) Q6A E D9 GND GND ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Function Table RESET DCS0 DCS1 ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity and Standby Function Table RESET DCS0 DCS1 ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Terminal Functions Terminal Name Characteristics GND REV CLK Differential Input CLK Differential Input C RESET CSGEN D1 - D28 DCS0, DCS1 DCKE0, DCKE1 DODT0, DODT1 PAR_IN Q1 - Q28 QCS0, ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Operating Characteristics, T The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Timing Requirements Over Recommended Operating Free-Air Temperature Range Symbol Parameter f Clock Frequency CLOCK t Pulse Duration, CLK, CLK HIGH or LOW W 1,2 t Differential Inputs Active Time ACT 1,3 t Differential ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET CSGEN DCS0 DCS1 CLK CLK t ACT Dn, DODTn, DCKEn Qn, QODTn, QCKEn PARIN QERR NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing NOTE: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET CSGEN DCS0 DCS1 CLK CLK Dn, DODTn, DCKEn Qn, QODTn, QCKEn PARIN QERR NOTE: 1.After RESET is switched from LOW to HIGH, all data and clock inputs signals must be ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT CLK Out CLK Inputs CLK Test Point R 100 L = Test Point Simulation Load Circuit LVCMOS RESET Input t ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT Out Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% 20% dv_f dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Ordering Information IDT XX SSTUBF XX Temp. Range Family 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 XXX XX X Device Type Package Shipping Carrier 8 BKG 868A COMMERCIAL TEMPERATURE GRADE Tape ...
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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...