SI5351A-A-GMR Silicon Laboratories, SI5351A-A-GMR Datasheet - Page 34

• Manufacturer Part Number: SI5351A-A-GMR
• Description: Control: I2C; Reference Inputs: 1; Clock Outputs: 8; Input Frequency (MHz): 25/27 MHz (Xtal); Output Frequency (MHz):...
• Manufacturer: Silicon Laboratories

Si5351A/B/C
Reset value = 0000 0000
34
Register 20. CLK4 Control
Name
3:2
1:0
Bit
Type
7
6
5
4
Bit
CLK4_IDRV[1:0] CLK4 Output Rise and Fall time / Drive Strength Control.
CLK4_SRC[1:0] Output Clock 4 Input Source.
CLK4_PDN
CLK4_PDN
MS4_SRC
CLK4_INV
MS4_INT
Name
R/W
D7
MS4_INT
R/W
Clock 4 Power Down.
This bit allows powering down the CLK4 output driver to conserve power when the out-
put is unused.
0: CLK4 is powered up.
1: CLK4 is powered down.
MultiSynth 4 Integer Mode.
This bit can be used to force MS4 into Integer mode to improve jitter performance.
Note that the fractional mode is necessary when a delay offset is specified for CLK4.
0: MS4 operates in fractional division mode.
1: MS4 operates in integer mode.
MultiSynth Source Select for CLK4.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 4 Invert.
0: Output Clock 4 is not inverted.
1: Output Clock 4 is inverted.
These bits determine the input source for CLK4.
00: Select the XTAL as the clock source for CLK4. This option by-passes both synthe-
sis stages (PLL/VCXO & MultiSynth) and connects CLK4 directly to the oscillator
which generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK4. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK4 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK4. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
D6
MS4_SRC
R/W
D5
Preliminary Rev. 0.95
CLK4_INV
R/W
D4
Function
CLK4_SRC[1:0]
D3
R/W
D2
CLK4_IDRV[1:0]
D1
R/W
D0