SI5351A-A-GMR Silicon Laboratories, SI5351A-A-GMR Datasheet
SI5351A-A-GMR
Related parts for SI5351A-A-GMR
SI5351A-A-GMR Summary of contents
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... Si5351 can generate any frequency up to 160 MHz on each of its outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide variety of applications. The Si5351A generates free-running clocks using an internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an internal VCXO and provides the flexibility to replace both free-running clocks and synchronous clocks ...
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... Si5351A/B/C 2 Preliminary Rev. 0.95 ...
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... Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP 10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP 11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP 12. Si5351A Pin Descriptions (10-Pin MSOP 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14. Package Outline (24-Pin QSOP 15. Package Outline (20-Pin QFN ...
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... Si5351A/B/C 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature T A Core Supply Voltage V DD Output Buffer Voltage V DDOx Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. ...
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... 10–90 KVL Vc = 10–90 3 – °C) Test Condition Min –0 Preliminary Rev. 0.95 Si5351A/B/C Min Typ Max Unit — — — 10 µs — 333 — ps/step –0.1 — –2.5 % ±0.1 — ...
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... Si5351A/B/C Table 5. Output Clock Characteristics (V = 2.5 V ±10%, or 3.3 V ±10 – ° Parameter Symbol Frequency Range F CLK Load Capacitance C L Duty Cycle Rise/Fall Time t f Output High Voltage V OH Output Low Voltage V OL Period Jitter J PER Period Jitter VCXO ...
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... V — — –10 10 — 4 DDI2C 25 35 Test Condition Package 10-MSOP Still Air 24-QSOP JA 20-QFN 10-MSOP Still Air 24-QSOP JC 20-QFN Preliminary Rev. 0.95 Si5351A/B/C Fast Mode Unit 400 kbps Min Max 2 –0.5 0 DDI2C 2 0 3.63 V DDI2C 0.1 — 0 0 DDI2C – ...
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... Si5351A/B/C Table 9. Absolute Maximum Ratings Parameter DC Supply Voltage Input Voltage Junction Temperature Soldering Temperature (Pb-free 2 profile) Soldering Temperature Time at 2 TPEAK (Pb-free profile) Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Detailed Block Diagrams XA OSC XB SDA I Interface SCL XA OSC XB A0 SDA Interface SCL OEB Control Logic SSEN Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices VDD Si5351A 3-Output PLL MultiSynth PLL MultiSynth MultiSynth R2 2 GND VDD Si5351A 8-Output MultiSynth ...
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... Si5351A/B/C XA OSC XB VC SDA Interface SCL OEB Control Logic SSEN XA OSC XB CLKIN SDA SCL Interface INTR Control OEB Logic Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices 10 VDD Si5351B MultiSynth R0 0 PLL MultiSynth R1 1 MultiSynth VCXO R2 2 MultiSynth R3 3 MultiSynth ...
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... Multi Synth 7 Figure 3. Si5351 Block Diagram Selectable internal Optional load capacitors Additional external 6 pF load capacitors (< 2 pF) Preliminary Rev. 0.95 Si5351A/B/C Output Stage VDDOA R0 CLK0 CLK1 R1 VDDOB R2 CLK2 CLK3 R3 VDDOC R4 CLK4 CLK5 R5 VDDOD R6 CLK6 CLK7 ...
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... Si5351A/B/C 3.1.2. External Clock Input (CLKIN) The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs. CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to 30 MHz. ...
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... OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before going into a disabled state. 3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread spectrum enabled ...
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... Si5351A/B Interface Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the interface. The following is a list of the common features that are controllable through the I summary of register functions is shown in Section 7. ...
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... A Data [7:0] A Data [7: Reg Addr +1 1 – Read 0 – Write A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition 2 Figure 10 Read Operation 2 C-Bus Standard. SDA timeout is supported for compatibility Preliminary Rev. 0.95 Si5351A/B ...
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... Si5351A/B/C 5. Configuring the Si5351 The Si5351 is a highly flexible clock generator which is entirely configurable through its I default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for applications that need a clock present at power-up (e ...
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... Use ClockBuilder (Registers 15-92 and 149-170) Desktop v3.1 or later Apply PLLA and PLLB soft reset Figure 12. I Disable Outputs 0x80 Set interrupt masks (see register 2 description) Reg. 177 = 0xAC Enable desired outputs (see Register Programming Procedure Preliminary Rev. 0.95 Si5351A/B/C 17 ...
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... VCXOs, and PLLs. 5.3. Replacing Crystals and Crystal Oscillators Using an inexpensive external crystal, the Si5351A can generate different free-running clock frequencies for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is also available for applications that require fewer clocks ...
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... CLK2 Multi 28.322 MHz Synth 2 CLK3 Multi 74.25 MHz Synth 3 PLL CLK4 Multi 74.25/1.001 MHz Synth 4 CLK5 Multi 24.576 MHz Synth 5 Synchronous Clocks Preliminary Rev. 0.95 Si5351A/B/C Ethernet PHY USB Controller HDMI Port Video/Audio Processor Ethernet PHY USB Controller HDMI Port Video/Audio Processor 19 ...
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... Si5351A/B/C 5.6. Replacing a Crystal with a Clock The Si5351 can be driven with a clock signal through the XA input pin. Note: Float the XB input while driving the XA input with a clock Figure 16. Si5351 Driven by a Clock Signal 5.7. HCSL Compatible Outputs The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1 ...
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... Unused CLKIN pin should be tied to GND. Unused XA/XB pins should be left floating. Refer to "5.6. Replacing a Crystal with a Clock" on page 20 when using clock input pin. Unused output pins (CLK0–CLK7) should be left floating. Unused VDDOx pins should be tied to VDD. Preliminary Rev. 0.95 Si5351A/B/C 21 ...
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... Si5351A/B/C 6.6. Trace Characteristics The Si5351A/B/C features various output current drives ranging from (default recommended to configure the trace characteristics as shown in Figure 18 when an output drive setting used. Figure 18. Recommended Trace Characteristics with 8 mA Drive Strength Setting Note: Jitter is only specified at 6 and 8 mA drive strength. ...
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... MS0_P3[7:0] R0_DIV[2:0] MS0_P1[15:8] MS0_P1[7:0] MS0_P2[15:8] MS0_P2[7:0] MS1_P3[15:8] MS1_P3[7:0] R1_DIV[2:0] MS1_P1[15:8] MS1_P1[7:0] MS1_P2[15:8] MS1_P2[7:0] MS2_P3[15:8] MS2_P3[7:0] R2_DIV[2:0] MS2_P1[15:8] MS2_P1[7:0] MS2_P2[15:8] MS2_P2[7:0] Preliminary Rev. 0.95 Si5351A/B REVID[1:0] CLK2_EN CLK1_EN CLK0_EN OEB_CLK2 OEB_CLK1 OEB_CLK0 PLLA_SRC 0 0 CLK0_IDRV[1:0] CLK1_IDRV[1:0] CLK2_IDRV[1:0] CLK3_IDRV[1:0] CLK4_IDRV[1:0] CLK5_IDRV[1:0] CLK6_IDRV[1:0] CLK7_IDRV[1:0] ...
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... Si5351A/B/C Register MS3_P3[19:16 MS4_P3[19:16 MS5_P3[19:16 93–164 PLL, MultiSynth, and output clock delay offset Configuration Registers. Use ClockBuilder Desktop Software to Determine These Register Values. 165 166 167 ...
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... LOL_B PLLB Loss Of Lock Status. Si5351A/C only. PLLB will operate in a locked state when it has a valid reference from CLKIN or XTAL. A loss of lock will occur if the frequency of the reference clock forces the PLL to operate outside of its lock range as specified in Table the reference clock fails to meet the minimum requirements of a valid input signal as specified in Table 4 ...
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... Si5351A/B/C Register 1. Interrupt Status Sticky Bit D7 D6 Name SYS_INIT_STKY LOL_B_STKY LOL_A_STKY LOS_STKY Type R/W R/W Reset value = 0000 0000 Bit Name 7 SYS_INIT_STKY System Calibration Status Sticky Bit. The SYS_INIT_STKY bit is triggered when the SYS_INIT bit (register 0, bit 7) is trig- gered high. It remains high until cleared. Writing this register bit will cause it to clear ...
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... CLKIN Loss Of Signal Mask (Si5351C Only). Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOS is asserted not mask the LOS interrupt. 1: Mask the LOS interrupt. 3:0 Reserved Leave as default R/W R/W Function Preliminary Rev. 0.95 Si5351A/B R/W R/W R/W R/W 27 ...
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... Si5351A/B/C Register 3. Output Enable Control Bit D7 D6 Name CLK7_OEB CLK6_OEB CLK5_OEB CLK4_OEB CLK3_OEB CLK2_OEB CLK1_OEB CLK0_OEB Type R/W R/W Reset value = 0000 0000 Bit Name 7:0 CLKx_OEB Output Disable for CLKx. Where Enable CLKx output. 1: Disable CLKx output. Register 9. OEB Pin Enable Control ...
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... Reserved Leave as default. 3 PLLB_SRC Input Source Select for PLLB. 0: Select the XTAL input as the reference clock for PLLB (Si5351A/C only). 1: Select the CLKIN input as the reference clock for PLLB (Si5351C only). 2 PLLA_SRC Input Source Select for PLLA. 0: Select the XTAL input as the reference clock for PLLA. ...
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... MS0 operates in fractional division mode. 1: MS0 operates in integer mode. 5 MS0_SRC MultiSynth Source Select for CLK0. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK0_INV Output Clock 0 Invert. 0: Output Clock 0 is not inverted. 1: Output Clock 0 is inverted. ...
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... MS1 operates in fractional division mode. 1: MS1 operates in integer mode. 5 MS1_SRC MultiSynth Source Select for CLK1. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK1_INV Output Clock 1 Invert. 0: Output Clock 1 is not inverted. 1: Output Clock 1 is inverted. ...
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... MS2 operates in fractional division mode. 1: MS2 operates in integer mode. 5 MS2_SRC MultiSynth Source Select for CLK2. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK2_INV Output Clock 2 Invert. 0: Output Clock 2 is not inverted. 1: Output Clock 2 is inverted. ...
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... MS3 operates in fractional division mode. 1: MS3 operates in integer mode. 5 MS3_SRC MultiSynth Source Select for CLK3. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK3_INV Output Clock 3 Invert. 0: Output Clock 3 is not inverted. 1: Output Clock 3 is inverted. ...
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... MS4 operates in fractional division mode. 1: MS4 operates in integer mode. 5 MS4_SRC MultiSynth Source Select for CLK4. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK4_INV Output Clock 4 Invert. 0: Output Clock 4 is not inverted. 1: Output Clock 4 is inverted. ...
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... MS5 operates in fractional division mode. 1: MS5 operates in integer mode. 5 MS5_SRC MultiSynth Source Select for CLK5. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK5_INV Output Clock 5 Invert. 0: Output Clock 5 is not inverted. 1: Output Clock 5 is inverted. ...
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... Set this bit according to ClockBuilder Desktop generated register map file. 5 MS6_SRC MultiSynth Source Select for CLK6. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK6_INV Output Clock 6 Invert. 0: Output Clock 6 is not inverted. 1: Output Clock 6 is inverted. ...
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... Set this bit according to ClockBuilder Desktop generated register map file. 5 MS7_SRC MultiSynth Source Select for CLK7. 0: Select PLLA as the source for MultiSynth0. 1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0. 4 CLK7_INV Output Clock 7 Invert. 0: Output Clock 7 is not inverted. 1: Output Clock 7 is inverted. ...
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... Si5351A/B/C Register 24. CLK3–0 Disable State Bit D7 D6 Name CLK3_DIS_STATE Type R/W Reset value = 0000 0000 Bit Name 7:0 CLKx_DIS_STATE Clock x Disable State. Where These 2 bits determine the state of the CLKx output when dis- abled. Individual output clocks can be disabled using register Output Enable Con- trol located at address 3 ...
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... Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS0_P3[7:0] Multisynth0 Parameter 3. This 20-bit number is an encoded representation of the denominator for the frac- tional part of the MultiSynth0 Divider MS0_P3[15:8] R/W Function MS0_P3[7:0] R/W Function Preliminary Rev. 0.95 Si5351A/B ...
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... Si5351A/B/C Register 44. Multisynth0 Parameters Bit D7 D6 Name R/W Type Reset value = xxxx xxxx Bit Name 7 Unused 6:4 R0_DIV[2:0] R0 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8 100b: Divide by 16 101b: Divide by 32 110b: Divide by 64 111b: Divide by 128 ...
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... Reset value = xxxx xxxx Bit Name 7:0 MS0_P2[15:8] Multisynth0 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the MultiSynth1 Divider MS0_P1[7:0] R/W Function Function MS0_P2[15:8] R/W Function Preliminary Rev. 0.95 Si5351A/B MS0_P2[19:16] R ...
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... Si5351A/B/C Register 49. Multisynth0 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS0_P2[7:0] Multisynth0 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the MultiSynth1 Divider. Register 50. Multisynth1 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx ...
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... Register 53. Multisynth1 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS1_P1[15:8] Multisynth1 Parameter 1. This 18-bit number is an encoded representation of the integer part of the MultiSynth1 divider R1_DIV[2:0] R/W R/W Function MS1_P1[15:8] R/W Function Preliminary Rev. 0.95 Si5351A/B MS1_P1[17:16] R/W R ...
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... Si5351A/B/C Register 54. Multisynth1 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS1_P1[7:0] Multisynth1 Parameter 1. This 18-bit number is an encoded representation of the integer part of the MultiSynth1 divider. Register 55. Multisynth1 Parameters Bit D7 D6 Name MS1_P3[19:16] Type Reset value = xxxx xxxx ...
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... Reset value = xxxx xxxx Bit Name 7:0 MS1_P3[7:0] Multisynth1 Parameter 3. This 20-bit number is an encoded representation of the denominator for the frac- tional part of the MultiSynth1 divider MS1_P2[7:0] R/W Function MS1_P3[15:8] R/W Function MS1_P3[7:0] R/W Function Preliminary Rev. 0.95 Si5351A/B ...
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... Si5351A/B/C Register 60. Multisynth2 Parameters Bit D7 D6 Name Type R/W Reset value = xxxx xxxx Bit Name 7 Unused 6:4 R2_DIV[2:0] R2 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8 100b: Divide by 16 101b: Divide by 32 110b: Divide by 64 111b: Divide by 128 ...
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... Reset value = xxxx xxxx Bit Name 7:0 MS2_P2[15:8] Multisynth2 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth2 divider MS2_P1[7:0] R/W Function R/W Function MS2_P2[15:8] R/W Function Preliminary Rev. 0.95 Si5351A/B MS2_P2[19:16] R ...
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... Si5351A/B/C Register 65. Multisynth2 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS2_P2[7:0] Multisynth2 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth2 divider. Register 66. Multisynth3 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx ...
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... Register 69. Multisynth3 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS3_P1[15:8] Multisynth3 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth3 divider R3_DIV[2:0] R/W R/W Function MS3_P1[15:8] R/W Function Preliminary Rev. 0.95 Si5351A/B MS3_P1[17:16] R/W R ...
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... Si5351A/B/C Register 70. Multisynth3 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS3_P1[7:0] Multisynth3 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth3 divider. Register 71. Multisynth3 Parameters Bit D7 D6 Name MS3_P3[19:16] Type Reset value = xxxx xxxx ...
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... Reset value = xxxx xxxx Bit Name 7:0 MS4_P3[7:0] Multisynth4 Parameter 3. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth4 divider MS3_P2[7:0] R/W Function MS4_P3[15:8] R/W Function MS4_P3[7:0] R/W Function Preliminary Rev. 0.95 Si5351A/B ...
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... Si5351A/B/C Register 76. Multisynth4 Parameters Bit D7 D6 Name Type R/W Reset value = xxxx xxxx Bit Name 7 Unused 6:4 R4_DIV[2:0] R4 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8 100b: Divide by 16 101b: Divide by 32 110b: Divide by 64 111b: Divide by 128 ...
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... Reset value = xxxx xxxx Bit Name 7:0 MS4_P2[15:8] Multisynth4 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth4 Divider MS4_P1[7:0] R/W Function R/W Function MS4_P2[15:8] R/W Function Preliminary Rev. 0.95 Si5351A/B MS4_P2[19:16] R ...
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... Si5351A/B/C Register 81. Multisynth4 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS4_P2[7:0] Multisynth4 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth4 divider. Register 82. Multisynth5 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx ...
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... Register 85. Multisynth5 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS5_P1[15:8] Multisynth5 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth5 divider R5_DIV[2:0] R/W R/W Function MS5_P1[15:8] R/W Function Preliminary Rev. 0.95 Si5351A/B MS5_P1[17:16] R/W R ...
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... Si5351A/B/C Register 86. Multisynth5 Parameters Bit D7 D6 Name Type Reset value = xxxx xxxx Bit Name 7:0 MS5_P1[7:0] Multisynth5 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth5 divider. Register 87. Multisynth5 Parameters Bit D7 D6 Name MS5_P3[19:16] Type Reset value = xxxx xxxx ...
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... This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be even integers greater than or equal to 6. All other divide values are invalid MS5_P2[7:0] R/W Function MS6_P1[7:0] R/W Function MS7_P1[7:0] R/W Function Preliminary Rev. 0.95 Si5351A/B ...
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... Si5351A/B/C Register 92. Clock 6 and 7 Output Divider Bit D7 D6 Name Type R/W Reset value = xxxx xxxx Bit Name 7 Reserved Leave as default. 6:4 R7_DIV[2:0] R7 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8 100b: Divide by 16 101b: Divide by 32 110b: Divide by 64 ...
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... CLK2_PHOFF[6:0] Clock 2 Initial Phase Offset. CLK2_PHOFF[6: unsigned integer with one LSB equivalent to a time delay of Tvco/4, where Tvco is the period of the VCO/PLL associated with this output CLK0_PHOFF[6:0] R/W R/W R/W Function CLK1_PHOFF[6:0] R/W R/W R/W Function CLK2_PHOFF[6:0] R/W R/W R/W Function Preliminary Rev. 0.95 Si5351A/B R/W R/W R R/W R/W R R/W R/W R/W 59 ...
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... Si5351A/B/C Register 168. CLK3 Initial Phase Offset Bit D7 D6 Name Type R/W R/W Reset value = 0000 0000 Bit Name 7 Reserved Only write 0 to this bit. 6:0 CLK3_PHOFF[6:0] Clock 3 Initial Phase Offset. CLK3_PHOFF[6: unsigned integer with one LSB equivalent to a time delay of Tvco/4, where Tvco is the period of the VCO/PLL associated with this output. ...
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... Type R/W R/W Reset value = 0000 0000 Bit Name 7 PLLB_RST PLLB_Reset. Writing this bit will reset PLLB. This is a self clearing bit (Si5351A/C only). 6 Reserved Leave as default. 5 PLLA_RST PLLA_Reset. Writing this bit will reset PLLA. This is a self clearing bit. 4:0 Reserved Leave as default ...
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... Si5351A/B/C 9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP) Si5351A 20-QFN Top View GND A0 3 PAD SCL 4 5 SDA Pin Number Pin Name 20-QFN 24-QSOP CLK0 13 21 CLK1 12 20 CLK2 9 15 CLK3 8 14 CLK4 19 3 CLK5 17 1 CLK6 ...
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... Output voltage supply pin for CLK0 and CLK1. See 6.2 P Output voltage supply pin for CLK2 and CLK3. See 6.2 P Output voltage supply pin for CLK4 and CLK5. See 6.2 P Output voltage supply pin for CLK6 and CLK7. See 6.2 P Ground Preliminary Rev. 0.95 Si5351A/B/C Si5351B 24-QSOP Top View 1 24 CLK6 2 23 CLK7 3 ...
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... Si5351A/B/C 11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP) Si5351C 20-QFN Top View GND INTR 3 PAD 4 SCL SDA 5 Pin Number Pin Name 20-QFN 24-QSOP CLK0 13 21 CLK1 12 20 CLK2 9 15 CLK3 8 14 CLK4 19 3 CLK5 17 1 CLK6 ...
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... Si5351A Pin Descriptions (10-Pin MSOP) Table 13. Si5351A 10-MSOP Pin Descriptions Pin Number Pin Name Pin Type* 10-MSOP CLK0 10 O CLK1 9 O CLK2 6 O SCL 4 I SDA 5 I/O VDD 1 P VDDO 7 P GND 8 P *Note Input Output Power Si5351A 10-MSOP ...
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... Si5351A/B/C 13. Ordering Information Si5351X An evaluation kit containing ClockBuilder Desktop software and hardware enable easy evaluatin of the Si5351A/B/C. The orderable part numbers for the evaluation kits are provided in Figure 20. Si535X Figure 20. Si5351A/B/C Evaluation Kit *Note: The 10-MSOP is only available in the Si5351A variant. ...
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... This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Min Nom — — 0.10 — 0.19 — 0.15 — 8.55 8.65 6.00 BSC 3.81 3.90 0.635 BSC 0.40 — 0.25 BSC 0 — 0.10 0.17 0.10 Preliminary Rev. 0.95 Si5351A/B/C Max 1.75 0.25 0.30 0.25 8.75 3.99 1. ...
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... Si5351A/B/C 15. Package Outline (20-Pin QFN) Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8. ...
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... This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Min Nom — — 0.00 — 0.75 0.85 0.17 — 0.08 — 3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.40 0.60 0.25 BSC 0 — — — — — — — — — Preliminary Rev. 0.95 Si5351A/B/C Max 1.10 0.15 0.95 0.33 0.23 0.80 8 0.20 0.25 0.10 0.08 69 ...
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... Si5351A/B OCUMENT HANGE IST Revision 0.1 to Revision 0.9 Updated max output frequency. Updated kV values in Table 3 on page 5. Updated "3.4. Spread Spectrum" on page 13. Added "5.1. Writing a Custom Configuration to RAM" on page 16. Added "5.7. HCSL Compatible Outputs" on page 20. Added "6.6. Trace Characteristics" on page 22. ...
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... N : OTES Preliminary Rev. 0.95 Si5351A/B/C 71 ...
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... Si5351A/B ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...