MN88413 PANASONIC [Panasonic Semiconductor], MN88413 Datasheet - Page 4

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MN88413

Manufacturer Part Number
MN88413
Description
Channel Decoder LSI for Digital Satellite Broadcast Reception
Manufacturer
PANASONIC [Panasonic Semiconductor]
Datasheet
MN88413
4
QPSK demodulator
Data rate
A/D converter resolution
Roll-off rate
AFC range
Synchronization establishment time
D/A converter used for LNB/AFC and AGC
Viterbi decoder
Frame synchronization detection, De-interleaver, Reed-Solomon decoding, and Energy dispersal
PLL circuit
CPU interface
Supply voltage
Power dissipation
Package
Specifications Overview
Linearity error
Differential linearity error
Input voltage level
Resolution
Linearity error
Differential linearity error
Output voltage level
: 990 mW (typical) [at VDD = 3.3 V, 60 Mbps, R = 7/8]
: Switchable between the DVB and the DSS specifications.
: Automatic detection of encoding ratios in the range 1/2 to 7/8.
: Auto-synchronous operation
: Switchable between the DVB and the DSS specifications.
: Reference clock input frequency: 4 MHz to 30 MHz
: I
: 3.3 V ±0.165 V
: QFP100-P-1818B (18
2
C bus interface
: 1 Mbps to 90 Mbps
: 6 bits
: ±0.5 LSB (typical)
: ±0.5 LSB (typical)
: 1.5 V [p-p] (typical) [On-chip self-bias circuit]
: Switchable between the DVB and the DSS specifications.
: ± (<symbol rate>/8)
: 100 ms or less.
: 8 bits
: ±0.5 LSB (typical)
: ±0.5 LSB (typical)
: 1.0 V [p-p] (typical) [0.0 V to 1.0 V]
18 mm)
Digital Bloadcast Reception LSI

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