PE4220-EK PEREGRINE [Peregrine Semiconductor Corp.], PE4220-EK Datasheet - Page 2

• Manufacturer Part Number: PE4220-EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

Figure 3. Pin Configuration (Top View)
Table 2. Pin Descriptions
Note 1: All RF pins must be DC blocked with an external
Table 3. DC Electrical Specifications
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
V
I
(V
Control Voltage High
Control Voltage Low
DD
DD
Pin
No.
DD
Power Supply Current
1
2
3
4
5
6
7
8
Power Supply Voltage
= 3V, V
Parameter
series capacitor or held at 0 V
CTRL
V
RFC
GND
CNTL
DD
Name
CTRL
GND
GND
GND
RFC
RF2
RF1
Pin
V
DD
= 3)
1
2
3
4
Nominal 3 V supply connection. A
bypass capacitor (100 pF) to the ground
plane should be placed as close as
possible to the pin
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Common RF port for switch (Note 1)
RF2 port (Note 1)
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
RF1 port (Note 1)
4220
0.7x V
Min
2.7
DD
DC
Description
.
8
7
6
5
Typ
3.0
30
RF1
GND
GND
RF2
0.3x V
Max
3.3
40
DD
Units
µA
V
V
V
Table 4. Absolute Maximum Ratings
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Control Logic Truth Table
Control Logic
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
control logic input voltage level exceeds V
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Symbol
V
V
T
T
P
V
ESD
DD
OP
ST
IN
I
Control Voltage
Document No. 70-0028-09 │ UltraCMOS™ RFIC Solutions
Power supply voltage
Voltage on any input
Storage temperature range
Operating temperature
range
Input power (50Ω)
ESD voltage (Human Body
Model)
Parameter/Conditions
RFC to RF1
RFC to RF2
DD
. For flexibility to
Signal Path
Min
-0.3
-0.3
-65
-40
DD
Product Specification
pin when the
Max
+ 0.3
V
150
250
4.0
85
25
DD
DD
PE4220
.)
Units
dBm
°C
°C
V
V
V