GL843 GENESYS [GENESYS LOGIC], GL843 Datasheet - Page 31

• Manufacturer Part Number: GL843
• Description: High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
• Manufacturer: GENESYS [GENESYS LOGIC]

©2000-2006 Genesys Logic Inc. - All rights reserved.
Offset 1Bh ……..……………………………………..…………..……..……..…. Default value = 8’h00
Offset 1Ch ……..……………………………………..…………..…....………. Default value = 8’h00
GRAYSET CHANSEL
7 GRAYSET
2-0 TGTIME[2:0] CCD line period selection.
3-0 ICGDLY[3:0]
CK4MTGL CK3MTGL CK1MTGL CKAREA
6 CHANSEL
5
3 CK4INV
2 CK3INV
1 LINECLP
0 RESERVED
4 ICGENB
7 CK4MTGL
6 CK3MTGL
5 CK1MTGL
4 CKAREA
3 MTLWD
R/W
R/W
BGRENB
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
R/W
R/W
0 Don’t reverse.
1 To reverse CCD Clock4.
0 Don’t reverse.
1 To reverse CCD Clock 3.
0 To select CCD pixel clamping.
1 To select CCD line clamping.
-
0 To disable ICG control.
1 To enable CCD shutter control signal ICG.
0 Disable toggle function in CCD clock 4.
1 Enable toggle function in CCD clock 4.
0 Disable toggle function in CCD clock 3.
1 Enable toggle function in CCD clock 3.
0 Disable toggle function in CCD clock 1 & 2.
1 Enable toggle function in CCD clock 1 &2.
0 This function is disabled.
1 CCD clock speed depends on CKSEL in scan area and DCKSEL in non-scan area.
0 Set the watchdog time-out as WDTIME[3:0].
1 Set the watchdog time-out as WDTIME[3:0] * 2.
000 1*LPERIOD(Reg38,Reg39)
001 2*LPERIOD
010 4*LPERIOD
011 8*LPERIOD
100 16*LPERIOD
101 32*LPERIOD
110 Reserved.
111 Reserved.
1
1
0
1
0
0
CCD ICG delay for rising/falling edge.
Select two channel output.
Fast true gray latch is 1 and 2 position.
The order of latching A/D data is B-G-R.
The order is R-G-B.
Select single channel output.
Fast true gray latch is 2 and 3 position.
BGRENB
R/W
R/W
ICGENB
R/W
R/W
ICGDLY3
MTLWD
R/W
R/W
TGTIME2 TGTIME1 TGTIME0
ICGDLY2
R/W
R/W
ICGDLY1
R/W
R/W
ICGDLY0
Page 31
R/W
R/W