PE3282A PEREGRINE [Peregrine Semiconductor Corp.], PE3282A Datasheet - Page 9

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PE3282A

Manufacturer Part Number
PE3282A
Description
1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis
Manufacturer
PEREGRINE [Peregrine Semiconductor Corp.]
Datasheet
Table 10. f
X = don’t care condition
Note 1: When the f
Note 2: Lock detect indicates when the VCO frequency is in “lock” . When PLL1 is in lock and PLL1 lock detect is selected, the f
will be HIGH, with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the f
pulses LOW. When PLL1/PLL2 lock detect is selected the f
are in lock.
Note 3: The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in
close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth
acquisition upon powering up.
Document 70/0002~07B
f
Output State
Disabled (Note 1)
PLL1 Lock detect (Note 2) (LD1)
PLL2 Lock detect (Note 2) (LD2)
PLL1/PLL2 Lock detect (Note 2)
PLL1 Reference divider output (f
PLL2 Reference divider output (f
PLL1 Programmable divider output (f
PLL2 Programmable divider output (f
Serial data out
Reserved
Reserved
Counter reset (Note 3)
o
LD
o
LD Programming Truth Table
o
LD is disabled the output is a CMOS LOW.
c
c
1)
2)
p
p
1)
2)
Peregrine Semiconductor Corporation
C
(PLL1 f
0
0
0
0
1
0
1
0
1
1
1
1
14
o
)
o
LD pin will be HIGH with narrow pulses LOW, only when both PLL1 and PLL2
C
(PLL1 LD)
0
1
0
1
X
X
X
X
0
0
1
1
13
C
(PLL2 f
0
0
0
0
0
1
0
1
1
1
1
1
24
o
)
C
(PLL2 LD)
0
0
1
1
0
0
1
1
0
1
0
1
23
®
o
LD pin will be HIGH, with narrow
1.1 GHz/510 MHz Dual PLL IC
o
LD pin

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