PE3282A PEREGRINE [Peregrine Semiconductor Corp.], PE3282A Datasheet - Page 2

• Manufacturer Part Number: PE3282A
• Description: 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

PE3282A
Figure 2. Pin Configuration TSSOP (JEDEC MO-153-AC)
Table 1. PE3282A Pin Description
Note 1: V
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DD
pins 1, 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
Pin Name
V
V
CP1
Gnd
f
f
Gnd
f
Gnd
f
Clock
Data
LE
Gnd
f
f
Gnd
CP2
V
V
in
in
r
o
in
in
DD
DD
DD
DD
LD
1
1
2
2
Type
(Note 1)
(Note 1)
Output
Input
Input
Input
Output
Input
Input
Input
Input
Input
Output
(Note 1)
(Note 1)
Description
Power supply voltage input. Input may range from 2.7 V to 3.6 V. A bypass capacitor should be
placed as close as possible to this pin and be connected directly to the ground plane.
Same as pin 1.
Internal charge-pump output for PLL1. For connection to a loop filter for driving the input of
an external VCO.
Ground.
Prescaler input from the PLL1 (RF) VCO. 1.1 GHz max frequency.
1.1 GHz prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is optional with
some loss of sensitivity.
Ground.
Reference frequency input.
Ground.
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect
signals, and data out of the shift register. CMOS output (see Table 10, f
Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the
21-bit shift register. A pull-down resistor is recommended.
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
A pull-down resistor is recommended.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is
loaded into one of the four appropriate latches (as assigned by the control bits). A pull-down
resistor is recommended.
Ground.
510 MHz prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is optional with
some loss of sensitivity.
Prescaler input from the PLL2 (IF) VCO. 510 MHz max frequency.
Ground.
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of
an external VCO.
Same as pin 1.
Same as pin 1.
Gnd
f
Gnd
Gnd
V
V
CP1
o
f
f
DD
LD
DD
in
in
f
1
1
r
10
1
6
2
3
4
5
7
8
9
20
19
18
16
15
14
13
12
11
17
V
V
CP2
Gnd
f
Gnd
LE
Data
Clock
f
in
in
DD
DD
2
2
o
LD Programming
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