PE3282A PEREGRINE [Peregrine Semiconductor Corp.], PE3282A Datasheet - Page 8

• Manufacturer Part Number: PE3282A
• Description: 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

Programmable Modes
Several modes of operation can be programmed with bits C
charge pump high impedance, output of the f
modes is shown in Table 9. The truth table for the f
Table 9. PE3282A Programmable Modes
Note 1: The PLL1 power-down mode disables all of PLL1’s components except the R
with CP1 (pin 3) and f
16) becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R
and the f
times.
Note 2: The C
relationship presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
• When VCO1 (RF) slope is positive like (1), C
• When VCO1 (RF) slope is negative like (2), C
• When VCO2 (IF) slope is positive like (1), C
• When VCO2 (IF) slope is negative like (2), C
PE3282A
Programmable Divide Values
(R
Data is clocked into the 21-bit shift register, MSB first.
When LE is asserted HIGH, data is latched into the
registers addressed by the last two bits shifted into the
21-bit shift register, according to Table 7. For example, to
program the PLL1 (RF) swallow counter, A
bits shifted into the register (S
bit A
Table 8. For normal operation, S
Test bit) must be programmed to 0 even if PLL2 (IF) is not
used.
S
C
see
Table 10
C
see
Table 10
1
15
24
14
, R
1
2
counter would then be programmed according to
, F
o
1
LD output, causing f
, F
S
C
see
Table 10
C
see
Table 10
11
2
14
, A
23
13
and C
1
, A
2
in
21
, M
1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and f
bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 4. This
S
C
0 = PLL2 CP normal
1 = PLL2 CP High Z
C
0 = PLL1 CP normal
1 = PLL1 CP High Z
1
13
22
12
, M
2
r
)
(pin 8) and f
0
, S
16
1
) would be (1, 1). The 5-
of address (0, 0) (the
o
21
LD (pin 10) to become high impedance. The Serial Control Interface remains active at all
11
21
11
1
should be set HIGH.
should be set HIGH.
should be set LOW.
, the last two
should be set LOW.
S
C
0 = PLL2 Phase Detector inverted
1 = PLL2 Phase Detector normal
C
0 = PLL1 Phase Detector inverted
1 = PLL1 Phase Detector normal
12
21
11
o
(Note 2)
(Note 2)
LD pin and power-down modes. The truth table for the programmable
o
LD output is shown in Table 10.
10
- C
14
Table 8. PE3282A Counter Programming Example
and C
Figure 5. VCO Characteristics
Output
Frequency
VCO
Divide
Value
0
1
2
31
•
20
MSB
S
A
0
0
0
•
1
1
- C
11
14
counter and the reference frequency input buffer,
24
S
C
0 = PLL2 on
1 = PLL2 off
C
0 = PLL1 on
1 = PLL1 off
11
20
10
, including the phase detector polarity,
(Note 1)
(Note 1)
S
A
0
0
0
•
1
VCO Input Voltage
10
13
1
and R
S
A
0
0
0
•
1
9
12
2
, the reference frequency input,
S
0
1
1
S
A
0
0
1
1
•
8
11
S
0
0
0
LSB
S
A
0
1
0
•
1
7
10
(2) Negative Slope VCO
(1) Positive Slope VCO
Document 70/0002~07B
Address
S
1
1
1
1
1
1
1
in
2 (pin
S
1
1
1
1
1
1
0