IC62LV256L ICSI [Integrated Circuit Solution Inc], IC62LV256L Datasheet - Page 8

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IC62LV256L

Manufacturer Part Number
IC62LV256L
Description
32K x 8 Low Power SRAM with 3.3V
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
IC62LV256L
WRITE CYCLE NO. 2 (CE
8
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
15
20
25
ADDRESS
Order Part No.
IC62LV256L-15T
IC62LV256L-15J
IC62LV256L-20T
IC62LV256L-20J
IC62LV256L-25T
IC62LV256L-25J
D
OUT
WE
D
CE
IN
CE
CE
CE
CE Controlled)
Package
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
DATA UNDEFINED
t
SA
V
IH
.
(1,2)
t
HZWE
t
AW
t
t
SCE
PWE
t
WC
HIGH-Z
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
t
SD
15
20
25
DATA-IN VALID
Order Part No.
IC62LV256L-15TI
IC62LV256L-15JI
IC62LV256L-20TI
IC62LV256L-20JI
IC62LV256L-25TI
IC62LV256L-25JI
t
HA
t
t
HD
LZWE
Integrated Circuit Solution Inc.
Package
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
ALSR008-0A 10/5/2001

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