YSS943 YAMAHA [YAMAHA CORPORATION], YSS943 Datasheet - Page 13

• Manufacturer Part Number: YSS943
• Description: ADAMB Advanced Digital Audio Multi channel decode processor
• Manufacturer: YAMAHA [YAMAHA CORPORATION]

YSS944/943/940
(2) On-chip memory access (firmware download)
(a) Burst transfer mode
Access to on-chip memory is performed in 32-bit units via the microprocessor interface. Also, on-chip
memory access can be performed concurrently with register access.
methods prepared for this LSI are explained below.
When the IA carrier (PRGMOD[1:0] = 11) is used, instruction code/coefficient data firmware can be
downloaded in this mode. By using this mode, a large amount of data can be downloaded at high speeds
when initialization is executed or when the sampling frequency is changed. The features of the burst
transfer mode are as follows.
• During the transfer period, decoding is aborted and data is transferred at high speeds.
• Data transferred from the microprocessor can be received without handshaking.
• Both instruction code firmware and coefficient data firmware can be downloaded.
The microprocessor interface’s sequence in firmware downloading burst transfer mode is shown below.
[Access steps and statuses]
<1> Register setting:
<2> Start firmware download:
<3> Continuation and termination of firmware download:
<4> When this LSI has not been selected:
<5> Register setting:
automatically effected during the transfer period.
The microprocessor interface function change for the on-chip memory access start address (A in
figure) and on-chip memory access is set by register as shown below.
• Set the instruction code firmware download mode (IACNFG = 1)
• Change the firmware program mode to IA carrier (PRGMOD[1:0] = 11).
• Set the on-chip memory access start address IAA[20:0].
• Change the function of the microprocessor interface pin from register access to on-chip memory
• The nMICS pin is fixed at low level.
• Data is transferred LSB first, in 32-bit units.
• Data is written to on-chip memory when the rising edge of MISCK occurs for the 32nd bit of data
• Each time 32 bits of data are written, IAA[20:0] is automatically incremented. Accordingly, when
• When nMICS changes from low level to high level, firmware download ends and the
• When accessing non-consecutive on-chip memory addresses or when resuming firmware
• Set the instruction code firmware execution mode (IACNFG = 0).
• Report the existence of boot firmware to this LSI (DL = 1).
• Change the firmware program mode PRGMOD[1:0] from “IA carrier” to another mode.
nMICS
MISCK
MISI
MISO
access (IA = 1).
Once this setting is made, the microprocessor interface functions in firmware downloading burst
transfer mode until the nMICS pin is set to high level.
(D31 in the figure).
writing to consecutive addresses, only the data is transferred.
microprocessor interface returns to accessing registers.
downloading after an access interruption, be sure to set IAA[20:0] as described in <1> above.
After completing a firmware download, perform the following processing.
D4
D5
<1>
D6
D7
D0
A
D1
A
D2
A
D3
<2>
A
D28
A
D29
A
High-Z
D30
A
D31
A
A+1
D0
A+1
D1
A+1
D2
A+1
D3
<3>
A+n
D28
A+n
D29
The two firmware downloading
A+n
D30
A+n
D31
Don't care
Don't care
<4>
Muting is
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