YSS943 YAMAHA [YAMAHA CORPORATION], YSS943 Datasheet - Page 11

• Manufacturer Part Number: YSS943
• Description: ADAMB Advanced Digital Audio Multi channel decode processor
• Manufacturer: YAMAHA [YAMAHA CORPORATION]

YSS944/943/940
• Audio interface
• Audio data output channel control
• Bypass
• User mute
• External memory interface
• Input delay (lip sync)
• Output delay
• Stream detection
• Auto mute
• Status ports
• General purpose I/O port
• Internal operating clock generation
• Power-up/power-down
- Master clock, bit clock, word clock, and four serial data (8ch) for input and output are provided
- Various audio interface formats are supported.
- The bit clock rate is fixed to 64 fs.
- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz,
- The bit clock and word clock on the output side have switchable input/output, and can therefore be
- A clock divider/switching function is included to enable adjustment of the input/output sampling
- Audio output data can be output to any of the channels for the SDO3 to SDO0 pins.
- Output of SDI data to SDO can bypass the internal core logic.
- Output channels can be muted via the microprocessor interface.
- Up to 4 Mb of SRAM can be connected for input delay and/or output delay.
- Access time can be adjusted via register settings.
- Input delay for adjusting synchronization between video and audio can be implemented when using
- 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 192 kHz can be
- 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 96 kHz can be
- Encoding format detection
- Zero detection
- Input sampling frequency detection
- All channels are muted automatically by detection of noise generation factor.
- Consecutive-zero data input detection:
- Auto mute period output:
- Interrupt request output:
- 8 general purpose I/O ports are available.
- Input and output mode can be switched by register setting.
- Generates the high-speed internal operating clock by on-chip PLL.
- Enables power-up/power-down control of the LSI via register settings.
external memory.
implemented without using external memory (some exceptions).
implemented using external memory.
respectively.
176.4 kHz, and 192 kHz.
used as either master or slave.
frequency for DTS 96/24, etc.
1 pin.
1 pin.
1 pin.
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