PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 54

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

10.4
10.4.1
10.4.2
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Memory Switch Units
The Memory Switch Unit blocks, IMSU and OMSU, provide DS0 or column switching of the
SBI336 or 77.76 MHz TelecomBus. Any input byte (or column) can be switched to any output
byte (or column). Four bits of CAS and three or four bits of control information are switched
along with the data byte. In SBI336 mode, the control signals are PL, V5 and JUST_REQ. In
TelecomBus mode, the control signals are PL, TPL, V5 and TAIS.
In DS0 switch mode, the data entering the MSU is stored in two alternating pages of memory.
Each page contains one complete frame (9720 bytes) of data. One of these alternating pages is
currently filling while the other is currently full. Data exiting the MSU is extracted from the
currently full page. As a consequence, the MSU imposes a nominal switching latency of 1
frame (125us). The selection of bytes to fill each output port requires a switching connection
memory. Control is required for each of the 9720 bytes in the output SBI336 frame. Complete
specification of an output byte requires 14 bits to specify which of the 9720 input bytes to use.
Dual copies of this control memory are required to provide hitless frame boundary switchover.
In column switch mode, the same switching principle described above is used, but less memory is
required. Data entering the MSU is stored in two alternating pages of memory. Each page
contains one row (1080 bytes) of data. In this mode, the nominal latency is 1 row if a frame (<15
µs). The switching connection memory for the output port requires control for each of the 1080
columns in the frame. Complete specification of an output column requires 11 bits to specify
which of the 1080 input columns to use. Dual copies of this control memory are required to
provide hitless frame boundary switchover.
Each MSU can be independently bypassed for reduced latency or debugging purposes.
Data Buffer
The Data Buffer block contains a double buffer structure for each frame consisting of a data byte,
4-bits of Channel Associated Signaling information and 4 bits of control information necessary
for identifying valid data and timing.
Connection Memory
The Connection Memory sub-block contains two pages of mapping configuration, page 0 and
page 1. One page is designated the active page and the other the stand-by page. Selection
between which page is to be active and which is to be stand-by is controlled by the ICMP signal
(for the IMSU) and OCMP signal (for the OMSU). The Connection Memory sub-block samples
the value on the ICMP signal at the C1 byte position as defined by the incoming frame pulse
signal, IC1FP. The Connection Memory sub-block samples the value on the OCMP signal at the
C1 byte position as defined by the receive serial interface frame pulse signal, RC1FP. Swaps
between the active/standby status of the two pages are synchronized to the first A1 byte of the
next frame or multiframe. This arrangement allows all devices in a cross-connect system to be
updated in a coordinated fashion. Consequently, DS0 streams or tributaries not being assigned
new positions are unaffected by page swaps.
The CMP input signals can be overridden by register configuration or by the SBI336S inband link
channel.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
53