PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 240

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
ERROR
CHANGEI
ERRORI
DLL_REFCLKI
SYSCLKI
The delay line error register bit (ERROR) indicates the DLL has run out of dynamic range.
When the DLL attempts to move beyond the end of the delay line, ERROR is set high. When
ERROR is high, the DLL cannot generate a output clock phase that causes the rising edge of
the reference clock to be aligned to the rising edge of SYSCLK. ERROR is set low, when the
DLL captures lock again.
ERROR is forced low when the OVERRIDE register is set high or when the VERN_EN
register is set high.
The delay line tap change event register bit (CHANGEI) indicates the CHANGE register bit
has changed value. When the CHANGE register changes from a logic zero to a logic one, the
CHANGEI register bit is set to logic one. The CHANGEI register bit is cleared immediately
after it is read, thus acknowledging the event has been recorded.
The delay line error event register bit (ERRORI) indicates the ERROR register bit has gone
high. When the ERROR register changes from a logic zero to a logic one, the ERRORI
register bit is set to logic one. If the ERRORE interrupt enable is high, the INT output is also
asserted when ERRORI asserts. The ERRORI register bit is cleared immediately after it is
read, thus acknowledging the event has been recorded.
The reference clock event register bit DLL_REFCLKI provides a method to monitor activity
on the reference clock. When the DLL reference clock changes from a logic zero to a logic
one, the DLL_REFCLKI register bit is set to logic one. The DLL_REFCLKI register bit is
cleared immediately after it is read, thus acknowledging the event has been recorded.
The system clock event register bit SYSCLKI provides a method to monitor activity on the
system clock. When the SYSCLK primary input changes from a logic zero to a logic one, the
SYSCLKI register bit is set to logic one. The SYSCLKI register bit is cleared immediately
after it is read thus acknowledging the event has been recorded.
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
239