PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 255

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

13.1
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Operation
There are several important aspects regarding the operation of NSE-based switch fabrics; these
are dealt with in turn in the following sections.
“C1” Synchronization.
Any NSE/SBS fabric can be viewed as a collection of five “columns” of devices:
Note that the devices in columns 0 and 4 are SBI bus devices while columns 1 and 3 are SBS or
SBSLITE devices. The dual column references refer to their two separate simplex flows. Path-
aligned STS-12 frames are pipelined through this structure in a regular fashion, under control of a
single clock source and frame pulse. There are latencies between these columns, and these
latencies may vary from path to path. The following design is used to accommodate these
latencies.
A timing pulse for SBI frames (2 KHz, 500= s) is generated and fed to each device in the fabric.
Each chip has a FrameDelay register (RC1DLY) which contains the count of 77.76 MHz clock
ticks that device should delay from the reference timing pulse before expecting the C1 characters
of the ingress STS-12 frames to have arrived. The base timing pulse is called t . The delays from t
based on the settings of the RC1DLY registers in the successive columns of the devices are called
t 0 , … t 4 . The first signal, t
used to instruct the ingress load devices (column 0) to start emitting an STS-12 frame (with its
special “C1” control character) at that time. t i is determined by the customer, based on device
and wiring delays to be approximately the earliest time that all “C1” characters will have arrived
in the ingress FIFOs of the t i column of devices. t i is selected to provide assurance that all “C1”
characters have arrived at the i
synchronize emission of the STS-12 frames. The ingress FIFOs permit a variable latency in C1
arrival of up to 24 clock cycles.
Note: SBS devices, being a memory switches, add a latency of one complete frame plus a few
clock ticks to the data.
column 0 consists of the ingress flow from the load devices (e.g., some SBI device)
column 1 consists of the ingress flow through the SBS devices
column 2 consists of the NSE-20G device
column 3 consists of the egress flow through the SBS devices
column 4 consists of the egress flow through the load devices (e.g. some SBI device)
1
(equal to t
th
column. The i
0
), determines the start of an STS-12 frame; this signal is
th
column of devices use the t i signal to
SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
254