DM9000BIEP DAVICOM [Davicom Semiconductor, Inc.], DM9000BIEP Datasheet - Page 34

• Manufacturer Part Number: DM9000BIEP
• Description: Industrial-grade Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Preliminary
Version: DM9000BI-13-DS-P02
January 17, 2008
17.15
17.14
17.13
17.12
17.11
-17.9
16.3
16.2
16.1
16.0
17.8
Bit
PHYADR[4
Bit Name
Reserved
100HDX
100FDX
10HDX
10FDX
SMRST
MFPSC
RLOUT
SLEEP
(PHYADR), PHY Address Bit 4:0
Default
1, RO
1, RO
1, RO
1, RO
0, RO
0, RW
1, RW
0, RW
0, RW
Industrial-grade Ethernet Controller with General Processor Interface
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
Reserved
Read as 0, ignore on write
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
Frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loop out Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Description
DM9000BI
34