DM9000BIEP DAVICOM [Davicom Semiconductor, Inc.], DM9000BIEP Datasheet - Page 25

• Manufacturer Part Number: DM9000BIEP
• Description: Industrial-grade Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.42 Memory data write command with address increment Register (F8H)
6.43 Memory data write address Register (FAH~FBH)
6.44 TX Packet Length Register (FCH~FDH)
6.45 Interrupt Status Register (FEH)
6.46 Interrupt Mask Register (FFH)
Preliminary
Version: DM9000BI-13-DS-P02
January 17, 2008
Bit
Bit
7:0
7:0
7:0
7:0
7:0
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RESERVED
RESERVED
LNKCHGI
MWCMD
LNKCHG
MDWAH
IOMODE
MDWAL
UDRUNI
UDRUN
TXPLH
TXPLL
Name
Name
Name
Name
Name
ROOI
ROO
ROS
PAR
ROI
PRI
PTI
PR
PT
PS0,RW
PS0,RW
Default
Default
Default
X,,R/W
X,R/W
X,WO
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
PS0,RW/C1
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
Default
Default
T0, RO
RO
RO
Industrial-grade Ethernet Controller with General Processor Interface
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1 or 2, depends on
the operator mode. (8-bit or 16-bit respectively)
Memory Data Write_ address High Byte
Memory Data Write_ address Low Byte
TX Packet Length High byte
TX Packet Length Low byte
Transmit Under-run
Packet Transmitted
Packet Received
Enable Link Status Change Interrupt
Enable Transmit Under-run Interrupt
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
Enable Packet Received Interrupt
0 :
1:
Reserved
Link Status Change
Receive Overflow Counter Overflow
Receive Overflow
Enable the SRAM read/write pointer to automatically return to the start
address when pointer addresses are over the SRAM size. Driver needs to
set. When driver sets this bit, REG_F5 will set to 0Ch automatically
Reserved
16-bit mode
8-bit mode
Description
Description
Description
Description
Description
DM9000BI
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