K4D551638D SAMSUNG [Samsung semiconductor], K4D551638D Datasheet - Page 13

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K4D551638D

Manufacturer Part Number
K4D551638D
Description
256Mbit GDDR SDRAM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet

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K4D551638D-TC
AC CHARACTERISTICS
AC CHARACTERISTICS (I)
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
CK cycle time
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data output hold time from DQS
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge
@Normal Precharge
Last data in to Row precharge
@Auto Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery +
Precharge
Exit self refresh to read command tXSR
Power down exit time
Refresh interval time
Parameter
Parameter
CL=3
CL=4
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
tHP
tQH
tRC
tRFC
tRAS
tRCDRD
tRCDW
tRP
tRRD
tWR
tWR_A
tCDLR
tCCD
tMRD
tDAL
tPDEX
tREF
Symbol
Symbol
tCHmin
tCLmin
3tCK
2.86
0.45
0.35
0.35
0.35
tHP-
0.35
+tIS
0.45
0.85
Min
200
Min
-0.6
-0.6
7.8
0.9
0.4
0.4
0.4
0.4
0.9
0.9
15
17
10
or
3
1
5
3
5
3
3
3
2
8
0
-
-
-2A
-2A
100K
Max
Max
0.55
0.55
0.35
1.15
0.6
0.6
1.1
0.6
0.6
0.6
0.6
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCHmin
tCLmin
3tCK
0.45
0.45
0.85
0.35
0.35
0.35
tHP-
0.35
Min
+tIS
Min
-0.6
-0.6
200
0.4
7.8
3.3
0.9
0.4
0.4
0.4
0.9
0.9
15
17
10
or
5
3
5
3
3
3
3
1
2
8
0
-
-
-33
-33
- 13 -
100K
Max
Max
0.55
0.55
0.35
1.15
0.6
1.1
0.6
0.6
0.6
0.6
0.6
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCHmin
tCLmin
3tCK
0.45
0.45
0.85
0.35
tHP-
Min
+tIS
Min
-0.6
-0.6
200
3.6
0.9
0.4
0.4
0.4
0.4
0.9
0.9
0.4
0.4
0.4
7.8
15
17
10
or
5
3
5
3
3
3
2
1
2
8
0
-
-
-36
-36
100K
Max
0.55
0.55
1.15
Max
0.6
0.6
0.4
1.1
0.6
0.6
0.6
0.6
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCHmin
tCLmin
3tCK
0.45
0.45
0.85
0.35
tHP-
+tIS
Min
-0.6
-0.6
Min
200
0.4
7.8
4.0
0.9
0.4
0.4
0.4
0.9
0.9
0.4
0.4
0.4
13
15
or
0
9
4
2
4
3
3
3
2
1
2
7
-
-
256M GDDR SDRAM
-40
-40
100K
Max
Max
0.55
0.55
1.15
0.6
0.4
1.1
0.6
0.6
0.6
0.6
0.6
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCHmin
tCLmin
Rev 1.8 (Oct. 2003)
3tCK
0.45
0.45
0.45
0.45
0.45
0.45
tHP-
0.45
+tIS
Min
-0.7
-0.7
Min
200
4.5
0.9
0.4
0.8
0.3
0.4
1.0
1.0
7.8
12
14
or
0
8
4
2
4
3
3
3
2
1
2
7
-
-
-45
-45
100K
Max
0.55
0.55
0.45
0.55
0.55
Max
0.7
0.7
1.1
0.6
1.2
0.6
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
Note
Note
1
1
1
1
1
1

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